公开(公告)号：DE3782558T2

公开(公告)日：1993-04-22

申请号：DE3782558

申请日：1987-05-22

Applicant: IBM

Inventor： CHAKRAVARTI SATYA NARAYAN ,  FONASH STEPHEN JOSEPH ,  MU XIAO-CHUN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/322 ,  H01L21/306

公开(公告)号：DE3071662D1

公开(公告)日：1986-08-21

申请号：DE3071662

申请日：1980-08-12

Applicant: IBM

Inventor： CHAKRAVARTI SATYA NARAYAN ,  HILTEBEITEL JOHN ANDREW

IPC: G11C17/00 ,  G11C5/02 ,  G11C17/08 ,  G11C17/12 ,  G11C17/16 ,  H01L21/8246 ,  H01L23/528 ,  H01L27/112 ,  H01L29/78 ,  H01L27/10

Abstract: An array of transistors suitable for use in a read only memory includes a plurality of spaced apart first conductive lines insulated from a semiconductor substrate and a plurality of spaced apart second conductive lines insulated from the substrate and from the first lines and disposed to intersect the first lines. Diffusion regions formed in the substrate as current carrying electrodes are defined by the first and second lines. A plurality of spaced apart third conductive lines are arranged to intersect the first and second lines and to connect to the diffusion regions. When the array is used in a read only memory, selected transistors of the array are made to have a different threshold voltage than that of the remaining transistors and the first and second lines form word lines, the third lines form bit or sense and ground lines and the diffusion regions form the source and drain regions of the transistors, with each diffusion region serving up to four transistors or cells.

公开(公告)号：DE3782558D1

公开(公告)日：1992-12-17

申请号：DE3782558

申请日：1987-05-22

Applicant: IBM

Inventor： CHAKRAVARTI SATYA NARAYAN ,  FONASH STEPHEN JOSEPH ,  MU XIAO-CHUN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/322 ,  H01L21/306

公开(公告)号：DE3377556D1

公开(公告)日：1988-09-01

申请号：DE3377556

申请日：1983-12-15

Applicant: IBM

Inventor： CHAKRAVARTI SATYA NARAYAN ,  GARBARINO PAUL LOUIS ,  MILLER DONALD ABRAM

IPC: H01L27/10 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108

Abstract: A method for leakage current characterization in the manufacture of dynamic random access memory cells is disclosed. The method includes the forming of two large gate-controlled diodes (A, B), each diode having a diffused junction which is substantially identical with that of the other diode. The gates (P1, P11) of the diodes have different perimeter-to-area ratios such that when testing is carried out, the leakage current components due to the contribution of the thin oxide area (14) can be isolated from the perimeter-contributed components of the isolating thick oxide (24). Dynamic testing can also be performed and, because of the small area for the test site, an "on chip" amplifier (T1, T2) can be provided at the site.

公开(公告)号：DE3071853D1

公开(公告)日：1987-01-15

申请号：DE3071853

申请日：1980-12-04

Applicant: IBM

Inventor： CHAKRAVARTI SATYA NARAYAN ,  HELLER LAWRENCE GRIFFITH ,  PRICER WILBUR DAVID

IPC: G11C11/409 ,  G11C11/4091 ,  G11C11/56 ,  G11C19/36 ,  H03K5/08 ,  G11C11/24

Abstract: A calibrated sensing system is provided for sensing charge in a storage medium, such as a storage capacitor (16), coupled to an access or bit/sense line (B/S) which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor (28) or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor (30) or potential well and compared with the unknown charge in the first potential well to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.