公开(公告)号：DE3171252D1

公开(公告)日：1985-08-08

申请号：DE3171252

申请日：1981-10-29

Applicant: IBM

Inventor： BARTHOLOMEW ROBERT FORBELL ,  GARBARINO PAUL LOUIS ,  GARDINER JAMES ROBERT ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/78 ,  H01L21/60

公开(公告)号：DE3278798D1

公开(公告)日：1988-08-25

申请号：DE3278798

申请日：1982-04-27

Applicant: IBM

Inventor： FATULA JOSEPH JOHN ,  GARBARINO PAUL LOUIS ,  SHEPARD JOSEPH FRANCIS

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/336 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/76 ,  H01L21/28 ,  H01L27/08

Abstract: A dielectrically isolated region (16) of a mono-crystalline substrate (10), which has a orientation, has a drain region of a field effect transistor (FET) in a surface having a (100) crystal orientation with the drain region being of opposite conductivity to the conductivity of the substrate (10). A gate channel extends into the substrate (10) from the drain region and is surrounded at its upper end by the drain region. An enlarged recess (37) extends into the substrate (10) beneath the gate channel and has its walls (38) of opposite conductivity to the conductivity of the substrate (10) to form a source region and a plate of a capacitor when the FET is part of a storage cell. The source region has its upper end surrounded by the gate channel.

公开(公告)号：DE3377556D1

公开(公告)日：1988-09-01

申请号：DE3377556

申请日：1983-12-15

Applicant: IBM

Inventor： CHAKRAVARTI SATYA NARAYAN ,  GARBARINO PAUL LOUIS ,  MILLER DONALD ABRAM

IPC: H01L27/10 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108

Abstract: A method for leakage current characterization in the manufacture of dynamic random access memory cells is disclosed. The method includes the forming of two large gate-controlled diodes (A, B), each diode having a diffused junction which is substantially identical with that of the other diode. The gates (P1, P11) of the diodes have different perimeter-to-area ratios such that when testing is carried out, the leakage current components due to the contribution of the thin oxide area (14) can be isolated from the perimeter-contributed components of the isolating thick oxide (24). Dynamic testing can also be performed and, because of the small area for the test site, an "on chip" amplifier (T1, T2) can be provided at the site.

公开(公告)号：DE3168886D1

公开(公告)日：1985-03-28

申请号：DE3168886

申请日：1981-07-14

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  GARBARINO PAUL LOUIS

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/321 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/90 ,  G11C11/40 ,  H01L23/52 ,  H01L29/52

公开(公告)号：DE3175450D1

公开(公告)日：1986-11-13

申请号：DE3175450

申请日：1981-06-05

Applicant: IBM

Inventor： FATULA JOSEPH JOHN ,  GARBARINO PAUL LOUIS

IPC: H01L29/74 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/749 ,  H01L29/78 ,  H01L29/94 ,  G11C11/24 ,  H01L21/82

公开(公告)号：DE2964588D1

公开(公告)日：1983-03-03

申请号：DE2964588

申请日：1979-03-29

Applicant: IBM

Inventor： GARBARINO PAUL LOUIS ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/762 ,  H01L21/31

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a dielectric layer of reflowed phosphosilicate glass (PSG) on top surfaces of a polycrystalline silicon layer which may be doped by phosphorous impurities diffusing from the PSG.