公开(公告)号：WO2005043614A3

公开(公告)日：2005-11-03

申请号：PCT/EP2004052704

申请日：2004-10-28

Applicant: IBM ,  IBM UK ,  CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

Inventor： CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L27/14

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了用于制造绝缘体上锗（GOI）衬底材料的方法，通过该方法制造的GOI衬底材料以及可以包括至少本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶上的掩埋绝缘体层以及位于掩埋绝缘体层顶上的含Ge层，优选纯Ge。 在本发明的GOI基板材料中，含Ge层也可以被称为GOI膜。 GOI膜是其中可以形成器件的本发明衬底材料的层。

公开(公告)号：JP2004214629A

公开(公告)日：2004-07-29

申请号：JP2003396383

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SADANA DEVENDRA K ,  BEDELL STEPHEN W ,  CHEN TZE-CHIANG ,  CHOE KWANG SU ,  FOGEL KEITH E

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/823807 ,  Y10S438/96

Abstract: PROBLEM TO BE SOLVED: To develop a new improved method for forming a relaxed SiGe-on-insulator substrate material which is thermodynamically stable with respect to the generation of a defect.
SOLUTION: Silicon to which tensile stress is applied is formed by epitaxially growing over the whole SiGe alloy layer. Silicon to which compressive stress is applied is formed by epitaxially growing over the whole porous silicon. A method of converting a patterned SOI region into patterned an SGOI (silicon-germanium ON oxide) by a SiGe/SOI heat mixing process for farther reinforcing the performance of a logic circuit in a padded DRAM is described in a preferred embodiment. The SGOI region in which Si is strained acts as a template for succeeding Si growth so that electrons and holes in the Si have higher mobilities.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003017709A

公开(公告)日：2003-01-17

申请号：JP2002123022

申请日：2002-04-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ASSADERAGHI FARIBORZ ,  CHEN TZE-CHIANG ,  MULLER PAUL K ,  EDWARD J NOWAKU ,  SHAHIDI GHAVAM G

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/41 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78675

Abstract: PROBLEM TO BE SOLVED: To provide a design capable of manufacturing a field-effect transistor which is fine in size and contains a sub-lithography channel length on an SOI wafer or a chip with a high degree of integration through a well-known and fully-developed process. SOLUTION: A short channel effect can be effectively restrained by the use of the impurity concentration of a steep gradient which can be accurately improved in shape and arranged at a proper position, and on the other hand, impurities are injected into a polysilicon seed adjacent to the conduction channel of a transistor and diffused into the conduction channel from the polysilicon seed to relax the allowance of a process. The polysilicon seed enables a polysilicon source/drain contact, which has a structure capable of reducing its current density and path length to an irreducible minimum and giving other mechanical advantages, to grow epitaxially from the polysilicon seed.

Abstract translation: 要解决的问题：提供一种能够制造尺寸精细并且在SOI晶片或具有高度集成度的芯片上的亚光刻通道长度通过公知的和完全的集成的场效应晶体管的设计 开发过程。 解决方案：通过使用可以精确改善形状并排列在适当位置的陡峭梯度的杂质浓度，可以有效地抑制短通道效应，另一方面，将杂质注入邻近的多晶硅晶种 晶体管的导电沟道，并且从多晶硅晶种扩散到导电沟道中以放宽工艺的余量。 多晶硅种子能够实现多晶硅源极/漏极接触，其具有能够将其电流密度和路径长度降低到不可约最小值并提供其它机械优点的结构，以从多晶硅种子外延生长。

公开(公告)号：JP2007184584A

公开(公告)日：2007-07-19

申请号：JP2006343832

申请日：2006-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN TZE-CHIANG ,  DORIS BRUCE B ,  VAMSI K PARUCHURI ,  MICHAEL PATRIK CHUDZIK ,  VIJAY NARAYANAN ,  MICHELLE L STEEN ,  ALESSANDRO CALLEGARI ,  KIM YOUNG-HEE ,  ZHANG YING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To prevent the depletion of the gate polysilicon of a CMOS by a gate electrode structure composed of a metal dielectric stack containing a large volume of potassium. SOLUTION: A semiconductor structure is provided by including an n-FET device and a p-FET device. At least either of the devices includes a gate electrode stack having a thin film of a silicon-containing electrode, i.e., polysilicon electrode and a first metal on the silicon-containing electrode. The other of the devices includes a gate electrode stack not having a thin film of a silicon-containing electrode but at least having a first metal gate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过由含有大量钾的金属电介质堆叠构成的栅电极结构来防止CMOS的栅极多晶硅的耗尽。 解决方案：通过包括n-FET器件和p-FET器件来提供半导体结构。 所述器件中的至少一个包括具有含硅电极的薄膜的栅电极堆叠，即多晶硅电极和含硅电极上的第一金属。 另一个器件包括不具有含硅电极薄膜但至少具有第一金属栅极的栅极电极堆叠。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003258126A

公开(公告)日：2003-09-12

申请号：JP2003031310

申请日：2003-02-07

Applicant: IBM

Inventor： CHEN TZE-CHIANG ,  HAN LIANG-KAI

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a protective structure for blocking the propagation of defects generated in a semiconductor device. SOLUTION: The protective structure is provided with a deep-trench isolation region 50 formed between a memory storing region 12 of the semiconductor device 10 and the logical operation circuit region 14 of the semiconductor device 10, while the deep-trench isolation region is filled with an insulation material. The deep-trench isolation region is formed below a shallow-trench isolation region 28 and the shallow-trench isolation region electrically separates a device included in the memory storage region 12 from a device included in the logical operation circuit region 14. According to this structure, the deep-trench isolation region blocks the propagation of crystalline defects generated in the logical operation circuit region into the memory storage region. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2007184583A

公开(公告)日：2007-07-19

申请号：JP2006343524

申请日：2006-12-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： VIJAY NARAYANAN ,  VAMSI K PARUCHURI ,  CHEN TZE-CHIANG ,  ALESSANDRO CALLEGARI ,  JOSEPH S NEWBURY ,  MICHELLE L STEEN ,  DORIS BRUCE B ,  MICHAEL PATRIK CHUDZIK ,  LINDER BARRY P ,  JOHN C ARNOLD

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS circuit which includes an n-FET gate stack having a gate dielectric and a metal gate conductor, and a p-FET gate stack having a gate dielectric layer and a silicon-containing gate conductor. SOLUTION: In the high-performance complementary metal oxide film semiconductor (CMOS) circuit, each semiconductor unit has at least the first gate stack and the second gate stack. The first gate stack is disposed on a first device region (e.g., n-FET device region) in a semiconductor board, and at least includes a gate dielectric layer 14, a metal gate conductor 16, and a silicon-containing gate conductor 18 that are laminated in increasing order. The second gate stack is disposed on a second device region (e.g., p-FET device region) in the semiconductor board; and at least includes a gate dielectric layer, and a silicon-containing gate conductor that are laminated in increasing order. The first and second gate stacks can be formed on the semiconductor board by a variety of integrated methods. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种CMOS电路，其包括具有栅极电介质和金属栅极导体的n-FET栅极堆叠，以及具有栅极介电层和含硅栅极导体的p-FET栅极堆叠 。 解决方案：在高性能互补金属氧化物半导体（CMOS）电路中，每个半导体单元至少具有第一栅极堆叠和第二栅极堆叠。 第一栅极堆叠设置在半导体板中的第一器件区域（例如，n-FET器件区域）上，并且至少包括栅极电介质层14，金属栅极导体16和含硅栅极导体18， 以增加的顺序层压。 第二栅极堆叠设置在半导体板中的第二器件区域（例如，p-FET器件区域）上; 并且至少包括以增加的顺序层叠的栅极介电层和含硅栅极导体。 第一和第二栅极堆叠可以通过各种集成方法形成在半导体板上。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006237183A

公开(公告)日：2006-09-07

申请号：JP2005048214

申请日：2005-02-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN TZE-CHIANG ,  PARKIN STUART S P

IPC: H01L27/105 ,  H01F10/16 ,  H01L21/8246 ,  H01L29/82

CPC classification number: G11C19/0808 ,  G11C11/14

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of manufacturing a magnetic data track necessary for building a magnetic shift register memory device. SOLUTION: The magnetic data track can be manufactured by forming a multilayered stack made by stacking a dielectric material and/or a silicon layer alternately. A via having a height of about 10 microns and a cross section of about 100 nm in length and width is formed in the multilayered stack of alternate layers by etching. Then, the via is filled up with a layer of alternately stacked ferromagnetic material and ferrimagnetic metal by electrical plating. The ferromagnetic material layer and the ferrimagnetic material layer are formed of magnetic materials having a different magnetization characteristic, a different magnetic exchange characteristic, or a different magnetic anisotropy. Due to the different magnetic characteristics, a magnetic wall can be fixed to the boundary between these layers. The magnetic wall is formed by the ferromagnetic material occurring on a notch or projection along the wall of the via or by the discontinuity in the ferromagnetic material. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造磁性移位寄存器存储器件所需的磁数据轨道的改进方法。 解决方案：可以通过形成通过交替堆叠电介质材料和/或硅层而制成的多层堆叠来制造磁数据轨道。 通过蚀刻在交替层的多层堆叠中形成具有约10微米的高度和长度和宽度约100nm的横截面的通孔。 然后，通过电镀填充一层交替层叠的铁磁材料和铁磁性金属。 铁磁材料层和铁磁材料层由具有不同磁化特性，不同磁交换特性或不同磁各向异性的磁性材料形成。 由于不同的磁特性，磁壁可以固定在这些层之间的边界上。 磁性壁由铁磁材料形成，该铁磁材料沿着通孔的壁的凹口或突起或由铁磁材料中的不连续性形成。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH10270388A

公开(公告)日：1998-10-09

申请号：JP7219498

申请日：1998-03-20

Applicant: SIEMENS AG ,  IBM

Inventor： MITWALSKY ALEXANDER R ,  CHEN TZE-CHIANG

IPC: H01L21/301 ,  H01L21/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a crack stopper which prevents the propagation of cracks and chips which occur when the effective area of an IC is diced. SOLUTION: A method for forming crack stopper is used for a semiconductor wafer carrying an integrated circuit which is formed so that the circuit may be separated by dicing a dielectric layer. In order to suppress the formation of a crack which occurs when the wafer is diced for isolating the integrated circuit, a discontinuity 250 is formed in a dielectric material in the edge section of a channel 218 without requiring any additional processing for the formation of the discontinuity 250. Therefore, the discontinuity 250 can be formed as part of the manufacturing process of the integrated circuit.

公开(公告)号：GB2493463A

公开(公告)日：2013-02-06

申请号：GB201214280

申请日：2011-05-18

Applicant: IBM

Inventor： GUO DECHAO ,  OLDIGES PHILIP ,  CHEN TZE-CHIANG ,  WANG YANFENG

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/49

Abstract: A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.

公开(公告)号：DE102013207490B4

公开(公告)日：2022-11-17

申请号：DE102013207490

申请日：2013-04-25

Applicant: IBM

Inventor： CHEN TZE-CHIANG ,  HONG AUGUSTIN J ,  KIM JEEHWAN ,  SADANA DEVENDRA K

IPC: H01L31/18 ,  C23C16/50 ,  H01L31/036

Abstract: Verfahren zum Bilden einer Photovoltaikeinheit (100), aufweisend:Bereitstellen eines Substrats (102); undAbscheiden einer Pufferschicht (105) zwischen einer transparenten Elektrode (104), die auf dem Substrat (102) ausgebildet ist, und einer p-leitenden Schicht (106) eines Photovoltaikstapels (106, 110, 112), wobei das Abscheiden der Pufferschicht (105) die Schritte umfasst:Durchführen einer Blitzabscheidung mit einer hohen Leistung von etwa 100 W/cm2zum Abscheiden eines ersten Teils (116) der Pufferschicht (105), um ein Kristallinitätsniveau und Leitfähigkeit der Pufferschicht (105) zu erhöhen; undDurchführen einer Abscheidung mit niedriger Leistung zum Abscheiden eines zweiten Teils der Pufferschicht (105) und zum Erhalten einer stärker amorphen Form, wobei der erste Teil (116) der Pufferschicht (105) an die p-leitende Schicht (106) angrenzt und der zweite Teil der Pufferschicht (105) an die transparente Elektrode (104) angrenzt, und wobei die Pufferschicht (105) einen Dotierstoff des p-Typs aufweist.