中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.018 seconds)

    Miniaturized semiconductor package arrangement
    1.
    发明专利
    Miniaturized semiconductor package arrangement 未知

    公开(公告)号：HK1027903A1

    公开(公告)日：2001-01-23

    申请号：HK00107091

    申请日：2000-11-08

    Applicant: IBM

    Inventor： CHEN WILLIAM TZE-YOU

    IPC: H01L21/60 ,  H01L23/31 ,  H01L

    Abstract: A semiconductor package arrangement and, more particularly, a light weight and miniaturized electronic package or module, wherein the dimensions between an integrated circuit comprising a semiconductor chip and those of a chip carrier have been optimized in order to provide for minimum weight and size relationships. Furthermore, disclosed is a method of forming the semiconductor package arrangement so as to produce a small, lightweight and essentially miniaturized chip-sized chip carrier package module. The chip carrier, which may be an organic laminate, multi-layer ceramic substrate or flexible substrate, as required by specific applications, is basically designed to possess overall smaller peripheral dimensions than those of the integrated circuit or semiconductor chip which is adapted to be mounted thereon. In essence, the chip carrier or substrate is electrically connected to the semiconductor chip through the intermediary of either solder bumps or a conductive adhesive, or other suitable flip chip connection methods. The utilization of an electronic package arrangement which comprises the mounting of a chip on a chip carrier or substrate, wherein the latter is of smaller peripheral dimensions than the semiconductor chip, and thereby eliminates in particular the edge stresses generated by the differentials in thermal expansion between the chip and chip carrier substrate, and in effect, reducing the previously generally encountered high mechanical stresses and extensive heat-induced warpage leading to potential failure of the electrical interconnects or solder joints.

    MINIATURIZED SEMICONDUCTOR PACKAGE ARRANGEMENT
    2.
    发明专利
    MINIATURIZED SEMICONDUCTOR PACKAGE ARRANGEMENT 未知

    公开(公告)号：MY123455A

    公开(公告)日：2006-05-31

    申请号：MYPI9904643

    申请日：1999-10-27

    Applicant: IBM

    Inventor： CHEN WILLIAM TZE-YOU

    IPC: H01L21/48 ,  H01L21/60 ,  H01L23/31

    Abstract: A SEMICONDUCTOR PACKAGE ARRANGEMENT (10) AND, MORE PARTICULARLY, A LIGHT WEIGHT AND MINIATURIZED ELECTRONIC PACKAGE OR MODULE, WHEREIN THE DIMENSIONS BETWEN AN INTEGRATED CIRCUIT COMPRISING A SEMICONDUCTOR CHIP (14) AND THOSE OF A CHIP CARRIER (12) HAVE BEEN OPTIMIZED IN ORDER TO PROVIDE FOR MINIMUM WEIGHT AND SIZE RELATIONSHIPS. FURTHERMORE, DISCLOSED IS METHOD OF FORMING THE SEMICONDUCTOR PACKAGE ARRANGEMENT SO AS TO PRODUCE A SMALL, LIGHTWEIGHT AND ESSENTIALLY MINIATURIZED CHIP-SIZED CHIP CARRIER PACKAGE MODULE. THE CHIP CARRIER, WHICH MAY BE AN ORGANIC LAMINATE, MULTI-LAYER CERAMIC SUBSTRATE OR FLEXIBLE SUBSTRATE, AS REQUIRED BY SPECIFIC APPLICATIONS, IS BASICALLY DESIGNED TO POSSESS OVERALL SMALLER PERIPHERAL DIMENSIONS THAN THOSE OF THE INTEGRATED CIRCUIT OR SEMICONDUCTOR CHIP WHICH IS ADAPTED TO BE MOUNTED THEREON. IN ESSENCE, THE CHIP CARRIER OR SUBSTRATE IS ELECTRICALLY CONNECTED TO THE SEMICONDUCTOR CHIP THROUGH THE INTERMEDIARY OF EITHER SOLDER BUMPS OR A CONDUCTIVE ADHESIVE (20, 36), OR OTHER SUITABLE FLIP CHIP CONNECTION METHODS. THE UTILIZATION OF AN ELECTRONIC PACKAGE ARRANGEMENT (10) WHICH COMPRISES THE MOUNTING OF A CHIP (14) ON A CHIP CARRIER OR SUBSTRATE (12), WHEREIN THE LATTER IS OF SMALLER PERIPHERAL DIMENSIONS THAN THE SEMICONDUCTOR CHIP, AND THEREBY ELIMINATES IN PARTICULAR THE EDGE STRESSES GENERATED BY THE DIFFERENTIALS IN THERMAL EXPANSION BETWEEN THE CHIP AND CHIP CARRIER SUBSTRATE, AND IN EFFECT, REDUCING THE PREVIOUSLY GENERALLY ENCOUNTERED HIGH MECHANICAL STRESSES AND EXTENSIVE HEAT-INDUCED WARPAGE LEADING TO POTENTIAL FAILURE OF THE ELECTRICAL INTERCONNECTS OR SOLDER JOINTS.(FIG. 1)

Patent Agency Ranking