公开(公告)号：EP1366512A4

公开(公告)日：2009-07-08

申请号：EP01987440

申请日：2001-12-19

Applicant: IBM

Inventor： WALKER GEORGE F ,  GOLDBLATT RONALD D ,  GRUBER PETER A ,  HORTON RAYMOND R ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  CHENG TIEN-JEN

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract translation: 描述了用于形成适用于引线键合和焊料凸点倒装芯片连接（例如可控塌陷芯片连接（C4））的公共输入 - 输出（I / O）位置的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易因结合力而损坏。 本发明通过在衬垫的顶表面上提供具有贵金属的部位，同时提供扩散阻挡层以维持金属互连的高导电性，从而降低了损坏的风险。 通过提供在衬底中形成的特征中选择性地沉积金属层的方法来减少用于在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸点连接，这为芯片互连选项提供了增加的灵活性，同时还降低了工艺成本。

公开(公告)号：JP2006059814A

公开(公告)日：2006-03-02

申请号：JP2005238111

申请日：2005-08-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BERNIER WILLIAM E ,  CHENG TIEN-JEN ,  COLE MARIE S ,  EICHSTADT DAVID E ,  FAROOQ MUKTA G ,  PHIZHIMONS JOHN A ,  LEWIS S GOLDMAN ,  KNICKERBOCKER JOHN U ,  LOPEZ TASHA E ,  WELSH DAVID J

IPC: H01R11/01

CPC classification number: H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a connector surrounded with a compressive material which connects a device with a support without separation.
SOLUTION: An unleaded connector is formed on the device, the unleaded connector is surrounded with a compressive film, the device is combined with the support, i.e. the unleaded connector connects the device with the support electrically, and a clearance between the support and the device is filled with an insulation underfill. A device supporting structure constituted of these and a forming method for it are disclosed.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种被压缩材料包围的连接器，该压缩材料将装置与支撑件连接而不分离。 解决方案：在设备上形成无铅连接器，无铅连接器被压缩膜包围，该装置与支撑件组合，即，无铅连接器将该装置与支撑件电连接，支撑件之间的间隙 并且该装置填充有绝缘底部填充物。 公开了一种由它们构成的装置支撑结构及其形成方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005057264A

公开(公告)日：2005-03-03

申请号：JP2004218340

申请日：2004-07-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG TIEN-JEN ,  EICHSTADT DAVID E ,  GRIFFITH JONATHAN H ,  KNARR RANDOLPH F ,  PETRARCA KEVIN S ,  QUON ROGER A

IPC: H01L21/60 ,  H01L21/44 ,  H01L23/48 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K3/3457 ,  H05K3/4007 ,  H01L2224/05099

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing fine pitch electric conduction pads for flip chip bonding (also referred to as bumps). SOLUTION: Solder bumps which connect an electron device with a substrate or another structure are formed, by plating copper pins of high aspect ratio on a supporting structure, enclosing the pins into barrier materials, plating over the barrier materials with solders, and then, reflowing the solders. This electric structure includes electrical connection members fitted so as to connect with another electric structure. The structure comprises a set of contacts in the electric structure, at least one interface layer attaching to the set of contacts, a set of pads which are disposed on the set of contacts and include the interface layer, a set of electric conduction pins directly attaching to the pads, barrier layers attaching to all exposure surfaces of the set of the pins, and solder layers which enclose the barrier layers. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于倒装芯片接合的细间距导电焊盘的方法（也称为凸块）。 解决方案：通过在支撑结构上镀覆高纵横比的铜销将电子器件与衬底或其他结构连接起来的焊料凸块，将引脚封装成阻挡材料，用焊料覆盖阻隔材料，以及 然后，回流焊接。 这种电气结构包括电连接构件，其被安装成与另一个电气结构连接。 该结构包括在电结构中的一组触点，至少一个界面层，附着到该组触点，一组焊盘，它们设置在触点组上，并包括界面层，一组导电引脚直接连接 连接到该组引脚的所有暴露表面的焊盘，阻挡层以及围绕阻挡层的焊料层。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005094013A

公开(公告)日：2005-04-07

申请号：JP2004269142

申请日：2004-09-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BIGGS JULIE C ,  CHENG TIEN-JEN ,  EICHSTADT DAVID E ,  FANTI LISA A ,  GRIFFITH JONATHAN H ,  KNARR RANDOLPH F ,  KNICKERBOCKER SARAH H ,  PETRARCA KEVIN S ,  QUON ROGER A ,  SAUTER WOLFGANG ,  SRIVASTAVA KAMALESH K ,  VOLANT RICHARD P

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a wire bond in an I/C chip. SOLUTION: This method comprises steps of: providing an I/C chip having a conductive pad for wire bonding and at least one dielectric material layer on the pad; forming an opening penetrating the dielectric material layer to expose a part of said pad; forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening; forming a seed layer on the first conductive layer, applying photoresist onto the seed layer; exposing the photoresist to light and developing the light-exposed photoresist; exposing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material inside the opening to expose the seed layer; coating at least one second conductive material layer on the seed layer inside the opening; and removing the first conductive layer on the dielectric layer around the opening. The present invention includes the structure obtained by the above method. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在I / C芯片中形成引线键合的方法。 解决方案：该方法包括以下步骤：提供具有用于引线接合的导电焊盘和衬垫上的至少一个电介质材料层的I / C芯片; 形成贯穿所述电介质材料层的开口以露出所述垫的一部分; 在所述垫的暴露表面和所述开口的表面上形成至少第一导电层; 在所述第一导电层上形成种子层，将光致抗蚀剂施加到种子层上; 将光致抗蚀剂曝光并显影曝光的光致抗蚀剂; 暴露围绕开口的种子层的表面; 去除暴露的种子层; 去除开口内的光致抗蚀剂材料以暴露种子层; 在开口内的种子层上涂覆至少一个第二导电材料层; 以及去除围绕开口的电介质层上的第一导电层。 本发明包括通过上述方法获得的结构。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004190129A

公开(公告)日：2004-07-08

申请号：JP2003389992

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG TIEN-JEN ,  FOWLER TODD ,  GIRI AJAY ,  NENADIC ANTON ,  SAMUEL BLESSEN ,  WONG KEITH KWONG HON

IPC: C25D7/12 ,  C25D5/00 ,  C25D5/02 ,  C25D17/10 ,  C25D17/12 ,  C25D21/12 ,  H01L21/288 ,  H05K3/24

CPC classification number: H01L21/2885 ,  C25D5/02 ,  C25D17/001 ,  C25D17/007 ,  C25D17/10 ,  C25D17/12 ,  H05K3/241

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving the electroplating on a substrate to be plated having a feature different in density, and a device therefor. SOLUTION: The method includes a step of preparing a plating bath having an anode and a step of immersing the substrate constituting a cathode in the plating bath separately from the anode. A second cathode including a screening part having an opening of different sizes coincident with a metal feature is arranged in such a state adjacent to the surface of the substrate and separated from the surface of the substrate between the substrate and the anode in the plating bath. The screening part has a larger size opening adjacent to a high density feature area to be plated and a smaller size opening adjacent to a low density feature area to be plated. The method includes a step of applying a voltage between the substrate and the anode and between the second cathode and the anode to allow an electric current to flow to the plating bath and a step of electroplating the metal feature different in density on the substrate. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：DE112014000384T5

公开(公告)日：2015-09-24

申请号：DE112014000384

申请日：2014-01-07

Applicant: IBM

Inventor： FITZSIMMONS JOHN A ,  CHENG TIEN-JEN ,  FAROOQ MUKTA G

IPC: H01L23/48

Abstract: Die vorliegende Erfindung stellt eine stabilisierte fein texturierte Metallmikrostruktur bereit, die eine dauerfeste aktivierte Fläche 310 bildet, die zum Bonden eines 3D-Stacked Chips verwendbar ist. Eine feinkörnige Schicht, die der Selbstheilung widersteht, ermöglicht ein Bonden von Metall auf Metall in moderater Zeit und Temperatur und mit einer höheren Prozessflexibilität.

公开(公告)号：DE112014000384B4

公开(公告)日：2021-12-30

申请号：DE112014000384

申请日：2014-01-07

Applicant: IBM

Inventor： CHENG TIEN-JEN ,  FAROOQ MUKTA G ,  FITZSIMMONS JOHN A

IPC: H01L21/60 ,  H01L23/48

Abstract: Ein Verfahren zum Ausbilden eines Metall-Bonds zwischen einer ersten Metallstruktur und einer zweiten Metallstruktur, das aufweist:Zusammenhalten der ersten Metallstruktur und der zweiten Metallstruktur bei weniger als 350 °C, um ein Metall-Bond an einer Schnittstelle zu bilden, wobei die Schnittstelle einen Metallabscheidungs-Inhibitor in einer ersten Konzentration in wenigstens einer Größenordnung höher als eine zweite Konzentration des Metallabscheidungs-Inhibitors in entweder der ersten Metallstruktur oder der zweiten Metallstruktur aufweist.

公开(公告)号：AU2003294403A1

公开(公告)日：2005-07-14

申请号：AU2003294403

申请日：2003-11-18

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  CHENG TIEN-JEN ,  KNICKERBOCKER SARAH H ,  VOLANT RICHARD P ,  WALKER GEORGE F

IPC: H01L21/302 ,  H01L21/44 ,  H01L21/461 ,  H01L21/48 ,  H01L21/50 ,  H01L23/485