公开(公告)号：EP1366512A4

公开(公告)日：2009-07-08

申请号：EP01987440

申请日：2001-12-19

Applicant: IBM

Inventor： WALKER GEORGE F ,  GOLDBLATT RONALD D ,  GRUBER PETER A ,  HORTON RAYMOND R ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  CHENG TIEN-JEN

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract translation: 描述了用于形成适用于引线键合和焊料凸点倒装芯片连接（例如可控塌陷芯片连接（C4））的公共输入 - 输出（I / O）位置的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易因结合力而损坏。 本发明通过在衬垫的顶表面上提供具有贵金属的部位，同时提供扩散阻挡层以维持金属互连的高导电性，从而降低了损坏的风险。 通过提供在衬底中形成的特征中选择性地沉积金属层的方法来减少用于在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸点连接，这为芯片互连选项提供了增加的灵活性，同时还降低了工艺成本。

公开(公告)号：EP2257968A4

公开(公告)日：2014-05-07

申请号：EP09724159

申请日：2009-01-29

Applicant: IBM

Inventor： HOVEL HAROLD J ,  HUANG QIANG ,  SHAO XIAOYAN ,  VICHICONTI JAMES ,  WALKER GEORGE F

IPC: H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  C30B29/02 ,  H01L21/306 ,  H01L29/06 ,  H01L31/06

CPC classification number: H01L31/18 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/06 ,  C30B29/40 ,  C30B29/52 ,  C30B29/60 ,  C30B29/605 ,  C30B33/10 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L31/0352 ,  H01L33/20

公开(公告)号：EP1668745A4

公开(公告)日：2008-12-03

申请号：EP03770552

申请日：2003-09-30

Applicant: IBM

Inventor： VOLANT RICHARD P ,  PETRARCA KEVIN S ,  WALKER GEORGE F

IPC: H01R12/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/18 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

公开(公告)号：WO2014165318A3

公开(公告)日：2014-12-31

申请号：PCT/US2014030991

申请日：2014-03-18

Applicant: IBM

Inventor： WALKER GEORGE F

IPC: B01D35/06

CPC classification number: G01N27/44704 ,  G01N27/44747

Abstract: A system of controlled translocation of macromolecules by gel electrophesis employs a funnel nanopore structure. A graphene portion is attached to a porous material layer including funnel-shaped pores such that the graphene portion blocks the side of the porous material layer having openings for smaller pores. A pair of electrical contacts is formed on the graphene portion. A dielectric material layer may be deposited to hold the graphene portion in place. A nanoscale hole is formed through the dielectric material layer and the graphene portion to provide a smallest opening in a funnel nanopore structure. The funnel nanopore structure is placed within a capsule configured for gel electrophoresis. A linear chain of molecules can pass through a funnel-shaped pore and the nanoscale hole during the gel electrophoresis. A graphene nanopore detector allows measurement of blockage current for sufficient resolution of base pairs in DNA's.

Abstract translation: 通过凝胶电穿孔控制大分子移位的系统采用漏斗状纳米孔结构。 石墨烯部分连接到包括漏斗形孔的多孔材料层，使得石墨烯部分阻挡具有用于较小孔的开口的多孔材料层的侧面。 在石墨烯部分上形成一对电触点。 可以沉积介电材料层以将石墨烯部分保持在适当位置。 通过介电材料层和石墨烯部分形成纳米尺度的孔，以在漏斗状纳米孔结构中提供最小的开口。 将漏斗状纳米孔结构置于配置用于凝胶电泳的胶囊内。 分子的线性链可以在凝胶电泳期间通过漏斗形孔和纳米级孔。 石墨烯纳米孔检测器允许测量阻塞电流以在DNA中的碱基对的足够分辨率。

公开(公告)号：AU2003294403A1

公开(公告)日：2005-07-14

申请号：AU2003294403

申请日：2003-11-18

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  CHENG TIEN-JEN ,  KNICKERBOCKER SARAH H ,  VOLANT RICHARD P ,  WALKER GEORGE F

IPC: H01L21/302 ,  H01L21/44 ,  H01L21/461 ,  H01L21/48 ,  H01L21/50 ,  H01L23/485

公开(公告)号：CA2098416A1

公开(公告)日：1994-04-28

申请号：CA2098416

申请日：1993-06-15

Applicant: IBM

Inventor： FREIERMUTH PETER E ,  GINN KATHLEEN S ,  HALEY JEFFREY A ,  LAMAIRE SUSAN J ,  LEWIS DAVID A ,  MILLS GAVIN T ,  REDMOND TIMOTHY A ,  TSANG YUK L ,  VAN HORN JOSEPH J ,  VIEHBECK ALFRED ,  WALKER GEORGE F ,  YANG JER-MING ,  LONG CLARENCE S

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/311 ,  H01L21/265 ,  H01L21/268 ,  H01L21/326 ,  H01L21/329 ,  H01L21/306 ,  H01L21/31 ,  H01L21/477 ,  H01L21/479 ,  H01L21/70

Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of rectifying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.

公开(公告)号：DE112012003274T5

公开(公告)日：2014-06-26

申请号：DE112012003274

申请日：2012-07-13

Applicant: IBM

Inventor： HARRER STEFAN ,  ROSSNAGEL STEPHEN M ,  ROYYURU AJAY K ,  WALKER GEORGE F ,  MARTYNA GLENN J ,  POLONSKY STANISLAV ,  LUAN BINQUAN ,  PENG HONGBO ,  STOLOVITZKY GUSTAVO A

IPC: G01N27/30

Abstract: Eine Technik zum Steuern der Bewegung von einem oder mehreren mit einem Polymer verbundenen geladenen Gebilden durch einen Nanokanal wird bereitgestellt. Ein erstes Reservoir und ein zweites Reservoir sind durch den Nanokanal verbunden. Eine Elektrodenanordnung ist entlang des Nanokanals positioniert, wobei das erste Reservoir, das zweite Reservoir und der Nanokanal mit Fluid gefüllt sind. Eine erste Elektrode befindet sich im ersten Reservoir und eine zweite Elektrode im zweiten Reservoir. Die erste und die zweite Elektrode sind so konfiguriert, dass sie das eine oder die mehreren mit dem Polymer verbundenen geladenen Gebilde in den Nanokanal lenken. Eine Elektrodenanordnung ist so konfiguriert, dass sie das eine oder die mehreren geladenen Gebilde in dem Nanokanal einschließt, wenn sie im Hinblick auf Einschließen gesteuert wird. Die Elektrodenanordnung ist so konfiguriert, dass sie das eine oder die mehreren geladenen Gebilde entlang des Nanokanals bewegt, wenn sie im Hinblick auf Bewegen gesteuert wird.

公开(公告)号：CA2098416C

公开(公告)日：1997-05-13

申请号：CA2098416

申请日：1993-06-15

Applicant: IBM

Inventor： FREIERMUTH PETER E ,  GINN KATHLEEN S ,  HALEY JEFFREY A ,  LAMAIRE SUSAN J ,  LEWIS DAVID A ,  MILLS GAVIN T ,  REDMOND TIMOTHY A ,  TSANG YUK L ,  VAN HORN JOSEPH J ,  VIEHBECK ALFRED ,  WALKER GEORGE F ,  YANG JER-MING ,  LONG CLARENCE S

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/311 ,  H01L21/265 ,  H01L21/268 ,  H01L21/326 ,  H01L21/329 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/477 ,  H01L21/479 ,  H01L21/70

Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of rectifying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.

公开(公告)号：GB2507706A

公开(公告)日：2014-05-07

申请号：GB201403277

申请日：2012-07-13

Applicant: IBM

Inventor： HARRER STEFAN ,  LUAN BINQUAN ,  MARTYNA GLENN J ,  PENG HONGBO ,  POLONSKY STANISLAV ,  ROSSNAGEL STEPHEN ,  ROYYURU AJAY K ,  STOLOVITZKY GUSTAVO ALEJANDRO ,  WALKER GEORGE F

IPC: G01N33/487 ,  B82Y15/00 ,  G01N27/327

Abstract: A technique for controlling the motion of one or more charged entities linked to a polymer through a nanochannel is provided. A first reservoir and a second reservoir are connected by the nanochannel. An array of electrodes is positioned along the nanochannel, where fluid fills the first reservoir, the second reservoir, and the nanochannel. A first electrode is in the first reservoir and a second electrode is in the second reservoir. The first and second electrodes are configured to direct the one or more charged entities linked to the polymer into the nanochannel. An array of electrodes is configured to trap the one or more charged entities in the nanochannel responsive to being controlled for trapping. The array of electrodes is configured to move the one or more charged entities along the nanochannel responsive to being controlled for moving.

公开(公告)号：CA2110472A1

公开(公告)日：1994-09-02

申请号：CA2110472

申请日：1993-12-01

Applicant: IBM

Inventor： BHATT ANILKUMAR C ,  BUDA LEO R ,  EDWARDS ROBERT D ,  HART PAUL J ,  INGRAHAM ANTHONY P ,  MARKOVICH VOYA R ,  MOLLA JAYNAL A ,  MURPHY RICHARD G ,  SAXENMEYER GEORGE J JR ,  WALKER GEORGE F ,  WHALEN BETTE J ,  ZARR RICHARD S

IPC: G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  G01R31/26

Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.