公开(公告)号：GB2578061B

公开(公告)日：2021-12-01

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：GB2581104B

公开(公告)日：2020-11-18

申请号：GB202007030

申请日：2018-10-23

Applicant: IBM

Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  CHUN WING YEUNG

IPC: H01L29/78

Abstract: A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

公开(公告)号：GB2581104A

公开(公告)日：2020-08-05

申请号：GB202007030

申请日：2018-10-23

Applicant: IBM

Inventor： CHEN ZHANG ,  TENKO YAMASHITA ,  CHUN WING YEUNG

IPC: H01L29/78

Abstract: A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.

公开(公告)号：GB2578061A

公开(公告)日：2020-04-15

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.