公开(公告)号：GB2581116A

公开(公告)日：2020-08-05

申请号：GB202008885

申请日：2018-12-14

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：GB2581116B

公开(公告)日：2021-03-03

申请号：GB202008885

申请日：2018-12-14

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：GB2571215A

公开(公告)日：2019-08-21

申请号：GB201906829

申请日：2017-10-25

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  HEMANTH JAGANNATHAN

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/306

Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less than 500°C on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500°C for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

公开(公告)号：GB2575598B

公开(公告)日：2021-10-06

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：GB2578061A

公开(公告)日：2020-04-15

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：GB2578061B

公开(公告)日：2021-12-01

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：GB2575598A

公开(公告)日：2020-01-15

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.