公开(公告)号：JP2005175483A

公开(公告)日：2005-06-30

申请号：JP2004353571

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLGAN EVAN G ,  FEGER CLAUDIS ,  GOTH GARY F ,  KATOPIS GEORGE A ,  MAGERLEIN JOHN H ,  SPROGIS EDMUND J

IPC: H01L23/34 ,  H01L21/50 ,  H01L21/56 ,  H01L23/10 ,  H01L23/12 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L23/3737 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To reduce the temperature of a hot spot of a chip by locally reducing the layer thickness of a compliant thermally conductive material on the chip.
SOLUTION: In an integrated circuit package structure within MCM or SCM, a compliant thermally conductive material is applied between a heat-producing integrated circuit and a substrate attached thereto. A thinner layer of the compliant thermally conductive material is arranged between the chip and the substrate in this region after assembling, and as a result, a raised region aligned to a high power density region higher than the average on the active front surface of the chip is defined at the backside of the chip so that the temperature of the "hot spot" on the chip is reduced. In an exemplary embodiment, the substrate comprises one of a heat sink, cooling plate, heat spreader, heat pipe, heat hat, package lid, and other cooling members.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过局部减小芯片上柔性导热材料的层厚来降低芯片热点的温度。 解决方案：在MCM或SCM中的集成电路封装结构中，将柔性导热材料施加在发热集成电路和附着于其之间的衬底之间。 柔性导热材料的较薄层在组装之后在该区域中布置在芯片和基板之间，结果是与高于芯片的有源前表面上的平均值的高功率密度区域对准的凸起区域 被限定在芯片的背面，使得芯片上的“热点”的温度降低。 在示例性实施例中，基板包括散热器，冷却板，散热器，热管，加热帽，封装盖和其它冷却构件中的一个。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004363594A

公开(公告)日：2004-12-24

申请号：JP2004159191

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLGAN EVAN G ,  DECUSATIS CASIMER M ,  JACOBOWITZ LAWRENCE ,  STIGLIANI JR DANIEL J

IPC: H01S5/022 ,  G02B6/43 ,  H01L31/0232 ,  H01S5/02 ,  H01S5/40 ,  H01S5/42 ,  H04B10/12 ,  H04B10/13 ,  H04B10/135 ,  H04B10/14

CPC classification number: H01S5/423 ,  G02B6/43 ,  H01L2224/16225 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02256

Abstract: PROBLEM TO BE SOLVED: To provide an integrated optical transducer assembly and a method of forming the same. SOLUTION: This integrated optical transducer assembly includes a substrate and a photoelectronic array attached to the substrate. The photoelectronic array further includes a plurality of individual sub-units which are bonded to each other to form a single array. The subunits include a defined number of individual photoelectronic elements associated with them, respectively. By using elastomeric material, an original alignment between the plurality of the subunits is maintained. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：DE112012004476T5

公开(公告)日：2014-07-10

申请号：DE112012004476

申请日：2012-10-10

Applicant: IBM

Inventor： GAYNES MICHAEL A ,  ZITZ JEFFREY A ,  COLGAN EVAN G

IPC: H05K7/20 ,  H01L23/34 ,  H01L23/40

Abstract: Eine Chipverkapselungsvorrichtung umfasst ein Substrat, einen Lastrahmen, welcher mit einem Klebstoffmaterial an dem Substrat befestigt ist, wobei der Lastrahmen so gebildet ist, dass er eine Öffnung definiert, und einen Halbleiterchip, welcher innerhalb der Öffnung an dem Substrat angebracht ist. Eine Dicke des Klebstoffmaterials zwischen dem Lastrahmen und dem Substrat variiert und wird so eingestellt, dass eine Fläche des Lastrahmens gegenüber dem Substrat im Wesentlichen parallel zu einer Fläche des Chips gegenüber dem Substrat angeordnet ist.

公开(公告)号：DE112012004476B4

公开(公告)日：2019-08-29

申请号：DE112012004476

申请日：2012-10-10

Applicant: IBM

Inventor： COLGAN EVAN G ,  GAYNES MICHAEL A ,  ZITZ JEFFREY A

IPC: H01L21/50 ,  H01L23/34 ,  H01L23/42 ,  H05K7/20

Abstract: Montageverfahren für ein Wärmesenken-Befestigungsmodul für eine Chipverkapselungsvorrichtung, das Verfahren aufweisend:- Befestigen eines Halbleiterchips (10) an einem Substrat (20), um einen Modul-Teilaufbau (30) zu bilden;- Anordnen eines Lastrahmens (90) und einer Distanzscheibe (80) in einer Halterung (40);- Auftragen von Klebstoff (100) auf den Lastrahmen (90);- belastbares Anordnen des Modul-Teilaufbaus mit der Chipvorderseite nach unten in der Halterung; und- Härten des Klebstoffs.

公开(公告)号：CA2358579C

公开(公告)日：2006-08-29

申请号：CA2358579

申请日：2001-10-05

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  SCHLEUPEN KAI R ,  COLGAN EVAN G

IPC: G02F1/1362 ,  H01L29/786 ,  G02F1/1368 ,  H01L33/00 ,  H01L49/02 ,  H05B33/12

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole dow n to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

公开(公告)号：GB2510300B

公开(公告)日：2015-12-02

申请号：GB201408501

申请日：2012-10-10

Applicant: IBM

Inventor： COLGAN EVAN G ,  GAYNES MICHAEL A ,  ZITZ JEFFREY A

IPC: H05K7/20 ,  H01L21/50 ,  H01L23/34 ,  H01L23/40 ,  H01L23/433

公开(公告)号：DE60108834T2

公开(公告)日：2006-01-19

申请号：DE60108834

申请日：2001-11-30

Applicant: IBM

Inventor： COLGAN EVAN G ,  SCHLEUPEN KAI R ,  TSUJIMURA TAKATOSHI

IPC: H01L29/786 ,  G02F1/1362 ,  G02F1/1368

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

公开(公告)号：DE60108834D1

公开(公告)日：2005-03-17

申请号：DE60108834

申请日：2001-11-30

Applicant: IBM

Inventor： COLGAN EVAN G ,  SCHLEUPEN KAI R ,  TSUJIMURA TAKATOSHI

IPC: H01L29/786 ,  G02F1/1362 ,  G02F1/1368

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

公开(公告)号：AT289079T

公开(公告)日：2005-02-15

申请号：AT01310043

申请日：2001-11-30

Applicant: IBM

Inventor： COLGAN EVAN G ,  SCHLEUPEN KAI R ,  TSUJIMURA TAKATOSHI

IPC: H01L29/786 ,  G02F1/1362 ,  G02F1/1368

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

公开(公告)号：CA2358579A1

公开(公告)日：2002-06-05

申请号：CA2358579

申请日：2001-10-05

Applicant: IBM

Inventor： COLGAN EVAN G ,  SCHLEUPEN KAI R ,  TSUJIMURA TAKATOSHI

IPC: H01L29/786 ,  G02F1/1362 ,  G02F1/1368 ,  H01L33/00 ,  H01L49/02 ,  H05B33/12

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole dow n to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.