公开(公告)号：JP2004334872A

公开(公告)日：2004-11-25

申请号：JP2004135680

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOSE PRADIP ,  BROOKS DAVID M ,  COOK PETER W ,  EMMA PHILIP G ,  GSCHWIND MICHAEL K ,  SCHUSTER STANLEY E ,  SRINIVASAN VIJAYALAKSHMI

IPC: G06F1/32 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption of a processor without tolerating the loss in performance and reduce leak power of the processor. SOLUTION: An integrated circuit device (IC) comprises a unit power adjusting mechanism, a leak reduction circuit which reduces LdI/de noise in the integrated circuit device to adjustably reduce leak power, and an activity prediction unit 130 which calls active/dormant states in the IC. The activity prediction unit 130 determines turn-on and turn-off times for IC unit. The activity prediction unit 130 controls a supply voltage selection circuit, selectively pass the supply voltage to a supply line at predicted turn-on time, and selectively inhibits the supply voltage at predicted turn-off time. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：AU2003269997A1

公开(公告)日：2005-04-14

申请号：AU2003269997

申请日：2003-08-26

Applicant: COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  IBM ,  BOSE PRADIP ,  CITRON DANIEL M

Inventor： COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  BOSE PRADIP ,  CITRON DANIEL M

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

公开(公告)号：FR2314617A1

公开(公告)日：1977-01-07

申请号：FR7611972

申请日：1976-04-16

Applicant: IBM

Inventor： COOK PETER W ,  SCHUSTE STANLEY E

IPC: H03M1/74 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H03M1/00 ,  H03K13/02

公开(公告)号：DE60327953D1

公开(公告)日：2009-07-23

申请号：DE60327953

申请日：2003-08-26

Applicant: IBM

Inventor： BOSE PRADIP ,  CITRON DANIEL M ,  COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V

IPC: G06F9/38 ,  G06F1/32

公开(公告)号：CA1075819A

公开(公告)日：1980-04-15

申请号：CA253587

申请日：1976-05-28

Applicant: IBM

Inventor： COOK PETER W ,  SCHUSTER STANLEY E

IPC: H03M1/74 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H03M1/00 ,  H03K13/02

Abstract: A C-2C analog-to-digital and digital-to-analog converter is described, the C-2C designation referring to the arrangement of capacitance in a capacitor ladder network. The capacitors are formed in a monolithic, multilayer structure which includes a substrate, diffusion regions in the substrate, a polysilicon layer and an aluminum layer wherein the capacitances are formed between the aluminum layer and the polysilicon layer and between the polysilicon layer and the diffusion region, and these capacitances have the ratio of 2C to C respectively. The capacitor ladder network formed in the multilayer structure can be trimmed or adjusted electrically after manufacture to obtain the desired tolerances.