公开(公告)号：CA2068796A1

公开(公告)日：1993-03-01

申请号：CA2068796

申请日：1992-05-15

Applicant: IBM

Inventor： CHOU NORMAN C ,  GUM PETER H ,  HOUGH ROGER E ,  KIM MOON J ,  MAZUROWSKI JAMES C ,  MCCAULEY DONALD W ,  SCALZI CASPER A ,  SCANLON JOHN F ,  WYMAN LESLIE W

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16

Abstract: P09-91-035 CPU EXPANSIVE GRADATION OF I/O INTERRUPTION SUBCLASS RECOGNITION A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

公开(公告)号：CA2100540A1

公开(公告)日：1994-04-20

申请号：CA2100540

申请日：1993-07-14

Applicant: IBM

Inventor： GEORGE JONEL ,  GLENDENING BETH A ,  GREENSTEIN PAUL G ,  HOUGH ROGER E ,  KUBALA JEFFREY P ,  RODELL JOHN T ,  SHAFA NORMAN E ,  STUCKI DAVID E

IPC: G06F9/46 ,  G06F9/445 ,  G06F9/50 ,  G06F13/14

Abstract: System and Method for Performing Resource Reconfiguration in a Computer System of the Invention A dynamic reconfiguration request for a change in a system's physical configuration is transmitted from a configuration controller to a hypervisor controlling operating systems executing in one or more partitions of the system. The hypervisor translates the physical reconfiguration request into a request for reconfiguration of logical resources known to the operating systems, first verifying it against an installation policy, and passes the requests to the operating systems in the partitions. The operating systems perform logical reconfiguration, then request physical reconfiguration of the hypervisor. The hypervisor initiates the physical reconfiguration through the configuration controller.

公开(公告)号：DE3479454D1

公开(公告)日：1989-09-21

申请号：DE3479454

申请日：1984-11-14

Applicant: IBM

Inventor： GUM PETER H ,  HOUGH ROGER E ,  TALLMAN PETER H ,  CURLEE THOMAS O

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/10 ,  G06F9/46 ,  G06F9/44

公开(公告)号：CA1213986A

公开(公告)日：1986-11-12

申请号：CA465434

申请日：1984-10-15

Applicant: IBM

Inventor： GUM PETER H ,  HOUGH ROGER E ,  TALLMAN PETER H ,  CURLEE THOMAS O III

IPC: G06F9/455 ,  G06F9/48 ,  G06F12/10 ,  G06F9/44

Abstract: The disclosed embodiments enable address translations for a virtual machine in the TLB of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided lo allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

公开(公告)号：CA1213066A

公开(公告)日：1986-10-21

申请号：CA469465

申请日：1984-12-06

Applicant: IBM

Inventor： HOUGH ROGER E

IPC: G06F12/00 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16 ,  G06F15/177

Abstract: NON-SPINNING TASK LOCKING USING COMPARE AND SWAP A method or controlling both shared and exclusive access for a resource in a multiprocessor system wherein a first-in/first-out queue is formed for tasks suspended while awaiting access and wherein access to the resource provides that control of access required for manipulation of the first-in/first-out queue which is not provided by the atomic nature of compare (double) and swap. Each member of the queue has indicators of the access it requested and of the next most recently enqueued member which has a corresponding indicator. A lockword is established having two parts, a lock flag indicating the status of the resource, whether available, under shared ownership or under exclusive ownership and a lock pointer pointing to the most recently enqueued task. In requesting or releasing access, an initial guess is made as to the value of the lockword and a projected lockword is calculated based on the guess. Then an atomic reference is made to the lockword during which no other multiprocessor has access to the lockword. During the atomic reference, the lockword is compared to the guess of the lockword and if the guess is correct, the lockword is replaced by the projected lockword which rearranges the queue for the requesting or releasing task. If the guess was incorrect, the value of the lockword is used to calculate another projected lockword. If another task can affect the next tasks to gain access, the process with the atomic reference is repeated until no intervening changes occur between atomic references.