公开(公告)号：BR112012031951A2

公开(公告)日：2018-03-06

申请号：BR112012031951

申请日：2011-06-10

Applicant: IBM

Inventor： ABHISHEK DUBE ,  DAE-GYU PARK ,  JEFFREY B JOHNSON ,  JINGHONG LI ,  JUDSON R HOLT ,  KEVIN K CHAN ,  ZHENGMAO ZHU

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：SG173260A1

公开(公告)日：2011-08-29

申请号：SG2010096741

申请日：2010-12-29

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  FREESCALE SEMICONDUCTOR INC ,  INFINEON TECHNOLOGIES CORP ,  FRANCK ARNAUD

Inventor： XIANGDONG CHEN ,  WEIPENG LI ,  MOCUTA ANDA C ,  DAE-GYU PARK ,  SHERONY MELANIE J ,  STEIN KENNETH J ,  HAIZHOU YIN ,  JIN-PING HAN ,  LAEGU KANG ,  MENG LEE YONG ,  WAY TEH YOUNG ,  VOON-YEW THEAN ,  DA ZHANG ,  ARNAUD FRANCK

Abstract: OF THE DISCLOSUREBALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERSAn integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Fig. 3

公开(公告)号：SG166729A1

公开(公告)日：2010-12-29

申请号：SG2010027910

申请日：2010-04-21

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： WEIPENG LI ,  DAE-GYU PARK ,  SHERONY MELANIE J ,  JIN-PING HAN ,  MENG LEE YONG

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.