公开(公告)号：GB2550740A

公开(公告)日：2017-11-29

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer(20) disposed on a substrate(10), a silicon germanium layer(30) disposed on the dielectric layer(20), and a strained semiconductor material layer(40) disposed directly on the silicon germanium layer(30), forming a plurality of fins(43, 45) on the SSOI structure, forming a gate structure(50) over a portion of at least one fin in a nFET region, forming a gate structure(60) over a portion of at least one fin in a pFET region, removing the gate structure(60) over the portion of the at least one fin in the pFET region, removing the silicon germanium layer(30) exposed by the removing, and forming a new gate structure(90) over the portion of the at least one fin in the pFET region, such that the new gate structure(90) surrounds the portion on all four sides.

公开(公告)号：GB2550740B

公开(公告)日：2020-05-20

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.