公开(公告)号：JP2007300103A

公开(公告)日：2007-11-15

申请号：JP2007113990

申请日：2007-04-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MOCUTA ANDA C ,  CHIDAMBARRAO DURESETI ,  DONATON RICARDO A ,  KERN RIM ,  ONSONGO DAVID MASARA

IPC: H01L21/20 ,  H01L21/338 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To reduce the formation of misfit dislocation that may reduce the charge mobility and device performance. SOLUTION: There is provided a method of manufacturing a semiconductor structure and a semiconductor device, more specifically, an N-type FET device. The device includes a stress receiving layer provided on a stress inducing layer via a material at an interface between the layers, which reduces the occurrence and propagation of misfit dislocation in the structure. The stress receiving layer includes silicon (Si), the stress inducing layer includes silicon-germanium (SiGe), and the material includes carbon given by doping both layers during the period of the formation of the device. The carbon can be doped over the entire SiGe layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：减少可能降低电荷迁移率和器件性能的失配位错的形成。 解决方案：提供一种制造半导体结构和半导体器件的方法，更具体地说，涉及一种N型FET器件。 该装置包括通过层之间的界面处的材料在应力诱导层上提供的应力接收层，这减少了结构中失配位错的发生和传播。 应力接收层包括硅（Si），应力诱导层包括硅锗（SiGe），并且该材料包括在器件形成期间通过掺杂两层给出的碳。 碳可以掺杂在整个SiGe层上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007158323A

公开(公告)日：2007-06-21

申请号：JP2006311038

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  KERN RIM ,  GREENE BRIAN J

IPC: H01L29/786 ,  H01L21/76 ,  H01L29/78

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/31675 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a stress-producing dielectric element which underlies the entire undersurface of an active semiconductor region.
SOLUTION: A compressive stress is applied to a channel region of a PFET by a structure including an independent stress-producing dielectric element that entirely underlies the bottom surface of an active semiconductor region in which a source, a drain and a channel region of the PFET are disposed. Specifically, the stress-producing dielectric element includes a region of a collapsed oxide which contacts the entire bottom surface of the active semiconductor region so that it has an area of the same spread as an area of the bottom surface. Bird beak-like oxide regions at the edges of the stress-producing dielectric element apply an upward force to the edges of the stress-producing dielectric element to provide a compressive stress to the channel region of the PFET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有产生应力的介电元件的晶体管，其在有源半导体区域的整个下表面的下方。 解决方案：通过包括独立的产生应力的电介质元件的结构将压应力施加到PFET的沟道区域，该电介质元件完全位于有源半导体区域的底表面之下，其中源极，漏极和沟道区域 的PFET。 具体而言，应力产生用电介质元件包括与活性半导体区域的整个底面接触的塌陷氧化物的区域，使得其具有与底面的面积相同的面积。 产生应力的电介质元件边缘处的鸟形喙状氧化物区向产生应力的电介质元件的边缘施加向上的力，以向PFET的沟道区提供压缩应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2550740B

公开(公告)日：2020-05-20

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

公开(公告)号：MY134036A

公开(公告)日：2007-11-30

申请号：MYPI20021065

申请日：2002-03-25

Applicant: IBM

Inventor： KERN RIM

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: A SOI STRUCTURE AND A METHOD FOT ITS FABRICATION, IN WHICH A STRAINED SILICON LAYER LIES DIRECTLY ON AN INSULATOR LAYER, CONTRARY TO THE PRIOR REQUIREMENT FOR STRAINED-Si LAYERS TO LIE DIRECTLY ON A STRAIN-INDUCING (E.G., SiGe) LAYER. THE METHOD GENERALLY ENTAILS THE FORMING A SILICON LAYER ON A STRAIN-INDUCING LAYER SO AS TO FORM A MULTILAYER STRUCTURE, IN WHICH THE STRAIN-INDUCING LAYER HAS A DIFFERENT LATTICE CONSTANT THAN SILICON SO THAT THE SILICON LAYER IS STRAINED AS A RESULT OF THE LATTICE MISMATCH WITH THE STRAIN-INDUCING LAYER. THE MULTILAYER STRUCTURE IS THEN BONDED TO A SUBSTRATE SO THAT AN INSULATING LAYER IS BETWEEN THE STRAINED SILICON LAYER AND THE SUBSTRATE, AND SO THAT THE STRAINED SILICON LAYER DIRECTLY CONTACTS THE INSULATING LAYER. THE STRAIN-INDUCING LAYER IS THEN REMOVED TO EXPOSE A SURFACE OF THE STRAINED SILICON LAYER AND YIELD A STRAINED SILICON-ON-INSULATOR STRUCTURE THAT COMPRISES THE SUBSTRATE, THE INSULATING LAYER ON THE SUBSTRATE, AND THE STRAINED SILICON LAYER ON THE INSULATING LAYER. AS A RESULT, THE METHOD YIELDS A STRAINED SILICON-ON-INSULATOR (SSOI) STRUCTURE IN WHICH THE STRAIN IN THE SILICON LAYER IS MAINTAINED BY THE SOI STRUCTURE. @ @ FIGURE 1

公开(公告)号：GB2550740A

公开(公告)日：2017-11-29

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer(20) disposed on a substrate(10), a silicon germanium layer(30) disposed on the dielectric layer(20), and a strained semiconductor material layer(40) disposed directly on the silicon germanium layer(30), forming a plurality of fins(43, 45) on the SSOI structure, forming a gate structure(50) over a portion of at least one fin in a nFET region, forming a gate structure(60) over a portion of at least one fin in a pFET region, removing the gate structure(60) over the portion of the at least one fin in the pFET region, removing the silicon germanium layer(30) exposed by the removing, and forming a new gate structure(90) over the portion of the at least one fin in the pFET region, such that the new gate structure(90) surrounds the portion on all four sides.

公开(公告)号：SG114496A1

公开(公告)日：2005-09-28

申请号：SG200104423

申请日：2001-07-20

Applicant: IBM

Inventor： KERN RIM

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/786

Abstract: A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.