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公开(公告)号：GB2628293A
公开(公告)日：2024-09-18
申请号：GB202409170
申请日：2022-12-06
Applicant: IBM
Inventor： ALEXANDER REZNICEK , MATTHIAS GEORG GOTTWALD , STEPHEN L BROWN
Abstract: A top pinned SAF-containing magnetic tunnel junction structure is provided that contains a coupling spacer composed of a paramagnetic hexagonal metal phase material that has a stoichiometric ratio of Me3X or Me2X, wherein Me is a magnetic metal having a magnetic moment and X is a metal that alloys with Me in a hexagonal phase and dilutes the magnetic moment of Me. In embodiments in which a Me3X coupling spacer is present, Me is cobalt, and X is vanadium, niobium, tantalum, molybdenum or tungsten. In embodiments in which a Me2X coupling spacer is present, Me is iron and X is tantalum or tungsten. The coupling spacer is formed by providing a material stack including at least a precursor paramagnetic hexagonal metal phase material forming multilayered structure that includes alternating layers of magnetic metal, Me, and metal, X, and then thermally soaking the material stack.
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公开(公告)号：GB2606919A
公开(公告)日：2022-11-23
申请号：GB202209965
申请日：2020-12-14
Applicant: IBM
Inventor： TAKASHI ANDO , RUILONG XIE , POUYA HASHEMI , ALEXANDER REZNICEK
IPC: H01L45/00
Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes (110, 108) electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material (106) is disposed between the top and bottom electrodes (110, 108) of the RRAM structure. The resistive switching material (106) exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers (324) are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer (326) formed on an upper surface of the dielectric spacers (324) and covering at least a portion of sidewalls of the top electrode (110). The passivation layer (326) is self-aligned with the first metal connection line.
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公开(公告)号：GB2604807A
公开(公告)日：2022-09-14
申请号：GB202207280
申请日：2020-10-23
Applicant: IBM
Inventor： ALEXANDER REZNICEK , MICHAEL RIZZOLO , RUILONG XIE
IPC: G11C11/16
Abstract: A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source/drain contact structure of a transistor, and a lower contact structure is connected to another of the source/drain contact structures of the transistor. In the present application, the MRAM device and the lower contact structure are present in the middle-of-the-line (MOL) not the back-end-of-the-line (BEOL). Moreover, the bottom electrode of the MRAM device, and a lower portion of the lower contact structure are present in a same dielectric material (i.e. a MOL dielectric material).
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公开(公告)号：GB2603608A
公开(公告)日：2022-08-10
申请号：GB202117331
申请日：2021-12-01
Applicant: IBM
Inventor： JINGYUN ZHANG , TAKASHI ANDO , CHOONGHYUN LEE , ALEXANDER REZNICEK
IPC: H01L29/06 , H01L21/02 , H01L21/28 , H01L21/3115 , H01L21/8238 , H01L29/423
Abstract: A method including forming nanosheet stacks 20 on a substrate 10, each nanosheet stack 20 including alternating layers of sacrificial semiconductor material and semiconductor channel material 18, removing sacrificial semiconductor material layers of the nanosheet stacks 20, forming a gate dielectric 24 surrounding the semiconductor channel layers 18 of the nanosheet stacks 20, and crystalizing the gate dielectric of a subset of the nanosheet stacks 20. The crystalized gate dielectric 32 may be formed by an annealing process. A dipole layer 34 may be formed over the gate dielectric 24 such that it surrounds the semiconductor channel layers 18, and the dipole material 34 may be diffused into the non-crystalized gate dielectric 24 of a second subset of stacks by a process of annealing. The different processes applied to the subsets of stacks may fabricate nanosheet transistors with different threshold voltages. The sacrificial semiconductor material may be silicon germanium, and the nanosheet stacks may form a FET or CMOS.
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公开(公告)号：GB2603442A
公开(公告)日：2022-08-03
申请号：GB202207430
申请日：2020-10-23
Applicant: IBM
Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.
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Patent Agency Ranking6.发明专利
公开(公告)号：GB2594428A
公开(公告)日：2021-10-27
申请号：GB202112164
申请日：2020-01-28
Applicant: IBM
Inventor： CHOONGHYUN LEE , TAKASHI ANDO , ALEXANDER REZNICEK , JINGYUN ZHANG , POUYA HASHEMI
Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.
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公开(公告)号：GB2615947B
公开(公告)日：2025-05-14
申请号：GB202307918
申请日：2021-10-21
Applicant: IBM
Inventor： BAHMAN HEKMATSHOARTABARI , ALEXANDER REZNICEK
Abstract: A Vertical Reconfigurable Field Effect Transistor (VRFET) has a substrate and a vertical channel. The vertical channel is in contact with a top silicide region that forms a lower Schottky junction with the vertical channel and a top silicide region that forms an upper Schottky junction with the vertical channel. The lower silicide region and the upper silicide region each form a source/drain (S/D) of the device. A lower gate stack surrounds the vertical channel and has a lower overlap that encompasses the lower Schottky junction. An upper gate stack surrounds the vertical channel and has an upper overlap that encompasses the upper Schottky junction. The lower gate stack is electrically insulated from the upper gate stack. The lower gate stack can electrically control the lower Schottky junction (S/D). The upper gate stack can electrically control the upper Schottky junction (S/D). The control of the lower Schottky junction (S/D) is independent and separate from the control of the upper Schottky junction (S/D). The upper gate stack is stacked above the lower gate stack enabling a reduced device footprint.
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公开(公告)号：GB2605288A
公开(公告)日：2022-09-28
申请号：GB202207233
申请日：2020-10-27
Applicant: IBM
Inventor： YOUNGSEOK KIM , INJO OK , ALEXANDER REZNICEK , SOON-CHEON SEO
Abstract: A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first area and contacts a surface of one of the second electrically conductive structures that contacts a surface of an underlying first electrically conductive structure, and the other of the sacrificial conductive pads has a second area, different from the first area, and contacts a surface of another of the second electrically conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and to convert a dielectric switching material of the patterned material stack into a conductive filament. After plasma treatment, the pair of sacrificial conductive pads is removed.
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9.发明专利
公开(公告)号：GB2594428B
公开(公告)日：2022-03-16
申请号：GB202112164
申请日：2020-01-28
Applicant: IBM
Inventor： CHOONGHYUN LEE , TAKASHI ANDO , ALEXANDER REZNICEK , JINGYUN ZHANG , POUYA HASHEMI
Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.
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公开(公告)号：GB2607740B
公开(公告)日：2025-02-12
申请号：GB202209975
申请日：2020-12-04
Applicant: IBM
Inventor： ALEXANDER REZNICEK , BAHMAN HEKMATSHOARTABARI , TAKASHI ANDO , KARTHIK BALAKRISHNAN
Abstract: A one-transistor-two-resistor (1T2R) resistive random access memory (ReRAM) structure, and a method for forming the same, includes forming a vertical field effect transistor (VFET) including an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing protruding regions of triangular shape bounded by planes that extend horizontally beyond the channel region. A ReRAM stack is conformally deposited on the VFET. The ReRAM stack includes an oxide layer located directly above the epitaxial region, a top electrode layer directly above the oxide layer and a metal fill above the top electrode layer. Each of the two opposing protruding regions of the epitaxial region acts as a bottom electrode for the ReRAM stack.
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