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    SRAM cell contg. self-retaining switches
    3.
    发明专利
    SRAM cell contg. self-retaining switches 未知

    公开(公告)号：DE4442358A1

    公开(公告)日：1995-06-08

    申请号：DE4442358

    申请日：1994-11-29

    Applicant: IBM

    Inventor： CHAPPELL BARBARA ALANE ,  DAVARI BIJAN ,  SAI-HALASZ GEORGE ANTHONY ,  TAUR YUAN

    IPC: G11C11/412 ,  H01L27/11 ,  H01L21/8244

    Abstract: Memory self-retaining switch formed on a semiconductor substrate comprises: (a) a gate insulating layer on the substrate; (b) shallow trenches formed through the insulating layer and in the substrate acting as insulation for the building block; (c) doped regions in the substrate between the shallow trenches, the doped regions defining source and drain regions; (d) gate stacks on top of regions of the oxide next to the doped regions; (e) a planarised insulator formed between the gate stacks; (f) openings in the planarised insulator for contacts to the doped regions and the gate stacks; (g) conducting material filling the openings to form contacts for the doped regions and the gate stacks; and (h) a patterned layer of a conducting material on top of the planarised insulator to connect selected contacts for wiring of the self-retaining switching. Also claimed is an SRAM-cell of six constructional units formed on a silicon substrate comprising: (i) a deep insulation trench formed in the substrate; (ii) a first self-retaining switch including two transistors (3,4) of p-conducting material which are formed on one side of the trench; (iii) a second self-retaining switch including two transistors (1,2) of n-conducting material formed on the second side of the trench opposite the first side; (iv) connector for cross-wise wiring of the transistors of the first self-retaining switch with the transistors of the second self-retaining switch, the connector comprising a conductor arranged perpendicular to the trench; and (v) two access transistors (5,6) arranged on the second side of the trench for access to the self-retaining switches. Further claimed is a process for formation of contacts on the diffusion regions and gate stacks on a semiconductor substrate comprising: (A) forming a conformal etch-stop layer on the substrate and the gate stacks; (B) forming a passivation layer on the etch-stop layer with a thickness sufficient to cover the gate stacks; (C) planarising the passivation layer to a height corresponding to the etch-stop layer; (D) forming first openings in the passivation layer and the gate stacks, the openings being so positioned that they border the diffusion regions and are of sufficient depth to make electrical contact to the gate stacks but not with the diffusion regions; (E) forming second opening in the passivation layer and the etch-stop layer bordering the gate stacks and being of sufficient depth to make contact with the diffusion regions, but being of insufficient depth on the gate stacks to make electrical contact with the gate stacks; and (F) filling the first openings and the second openings with a conducting material which forms the contacts.

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