公开(公告)号：JPH11317524A

公开(公告)日：1999-11-16

申请号：JP3111199

申请日：1999-02-09

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enable a field effect transistor to be accurately specified in channel length, lessened in source and drain resistance, and minimized in overlap capacitance, by a method wherein a gate hole is demarcated on a dielectric stack, an attached side wall layer is removed from a horizontal plane, and the gate hole is filled up with a gate conductor. SOLUTION: An etching window which is nearly equal in lateral dimension to a gate pillar that is specified in dimensions by a resist mask is provided to a dielectric stack which comprises nitride layers 31 and 38. An RIE process for forming a gate hole is used for transferring the etching window to the dielectric stack. Then, the gate hole is demarcated-by an RIE method, a side wall layer is attached and then removed from a horizontal plane. By this setup, the gate hole is lessened in length by a residual side wall spacer 61. Then, polysilicon is deposited inside the gate hole and on a dielectric stack uppermost layer 38, and the dielectric stack uppermost layer 38 is exposed by flattening the deposited polysilicon.

公开(公告)号：JPH11274496A

公开(公告)日：1999-10-08

申请号：JP3112599

申请日：1999-02-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： DAINE C BOYD ,  BURNS STUART M ,  HUSSEIN I HANAPHY ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66537

Abstract: PROBLEM TO BE SOLVED: To form a threshold adjusting implant located only under a channel, by implanting a threshold adjusting dopant through a gate hole or a punch- through adjusting dopant after defining the gate hole on a dielectric stack.
SOLUTION: After defining a gate hole 40 in a dielectric stack, either a threshold adjusting dopant or a punch-through dopant is implanted through the hole 40. Since the hole 40 allows the dopant to reach only a region just under the hole 40, the implantation of the dopant is effected by an accurately controlled method. The dimensions and shape of the hole 40 determine the dimensions and shape of the threshold adjusting implant. Therefore, the threshold adjusting implant located only under a channel can be formed.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了形成仅位于通道下方的阈值调节植入物，通过在限定电介质叠层上的栅极孔之后通过栅极孔或穿通调节掺杂剂注入阈值调节掺杂剂。 解决方案：在电介质叠层中定义栅极孔40之后，通过孔40注入阈值调节掺杂剂或穿通掺杂剂。由于孔40允许掺杂剂仅到达孔40正下方的区域，因此， 通过精确控制的方法实现掺杂剂的注入。 孔40的尺寸和形状决定了阈值调节植入物的尺寸和形状。 因此，可以形成仅位于通道下方的阈值调节植入物。

公开(公告)号：DE3479173D1

公开(公告)日：1989-08-31

申请号：DE3479173

申请日：1984-09-21

Applicant: IBM

Inventor： TAUR YUAN

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/302 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78

Abstract: A process for forming self-aligned complementary n* and p + source/drain regions in CMOS structures uses a single mask to form both the n - channel implant and then the p + channel implant. The mask comprises a resist pattern (20, Fig. 3) which covers the p + channel region while the n + source and drain regions (24, 26) are ion implanted. The resist mask is then used as a lift-off mask in order to cover the n + channel region while the p + source and drain regions (32, 34) are ion implanted.

公开(公告)号：SG71909A1

公开(公告)日：2000-04-18

申请号：SG1999000606

申请日：1999-02-15

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

公开(公告)号：DE4442358A1

公开(公告)日：1995-06-08

申请号：DE4442358

申请日：1994-11-29

Applicant: IBM

Inventor： CHAPPELL BARBARA ALANE ,  DAVARI BIJAN ,  SAI-HALASZ GEORGE ANTHONY ,  TAUR YUAN

IPC: G11C11/412 ,  H01L27/11 ,  H01L21/8244

Abstract: Memory self-retaining switch formed on a semiconductor substrate comprises: (a) a gate insulating layer on the substrate; (b) shallow trenches formed through the insulating layer and in the substrate acting as insulation for the building block; (c) doped regions in the substrate between the shallow trenches, the doped regions defining source and drain regions; (d) gate stacks on top of regions of the oxide next to the doped regions; (e) a planarised insulator formed between the gate stacks; (f) openings in the planarised insulator for contacts to the doped regions and the gate stacks; (g) conducting material filling the openings to form contacts for the doped regions and the gate stacks; and (h) a patterned layer of a conducting material on top of the planarised insulator to connect selected contacts for wiring of the self-retaining switching. Also claimed is an SRAM-cell of six constructional units formed on a silicon substrate comprising: (i) a deep insulation trench formed in the substrate; (ii) a first self-retaining switch including two transistors (3,4) of p-conducting material which are formed on one side of the trench; (iii) a second self-retaining switch including two transistors (1,2) of n-conducting material formed on the second side of the trench opposite the first side; (iv) connector for cross-wise wiring of the transistors of the first self-retaining switch with the transistors of the second self-retaining switch, the connector comprising a conductor arranged perpendicular to the trench; and (v) two access transistors (5,6) arranged on the second side of the trench for access to the self-retaining switches. Further claimed is a process for formation of contacts on the diffusion regions and gate stacks on a semiconductor substrate comprising: (A) forming a conformal etch-stop layer on the substrate and the gate stacks; (B) forming a passivation layer on the etch-stop layer with a thickness sufficient to cover the gate stacks; (C) planarising the passivation layer to a height corresponding to the etch-stop layer; (D) forming first openings in the passivation layer and the gate stacks, the openings being so positioned that they border the diffusion regions and are of sufficient depth to make electrical contact to the gate stacks but not with the diffusion regions; (E) forming second opening in the passivation layer and the etch-stop layer bordering the gate stacks and being of sufficient depth to make contact with the diffusion regions, but being of insufficient depth on the gate stacks to make electrical contact with the gate stacks; and (F) filling the first openings and the second openings with a conducting material which forms the contacts.

公开(公告)号：DE3582197D1

公开(公告)日：1991-04-25

申请号：DE3582197

申请日：1985-06-13

Applicant: IBM

Inventor： LIN BURN JENG ,  TAUR YUAN

IPC: H01L21/30 ,  G01J1/42 ,  G03F7/20 ,  G03F7/22 ,  G03F9/00 ,  H01L21/027 ,  G01M11/02 ,  H01L21/00

Abstract: In a lithographic apparatus, radiation from a source (2) passes through a mask (4), and an image is formed by a lens (6) on a semiconductor wafer (28). Radiation detectors in the wafer surface generate signals which are fed by conductors (13) to a computer (3). Tne computer regulates a Z-drive (7) and an X-Y drive (5) which adjust the wafer, lens and mask so that the computer receives a related sequence of signals. The radiation can be UV, optical E-beam, ion-beam or X-ray, and the computer measures performance characteristics of the apparatus, such as intensity, modulation transfer function (MTF), focus and alignment.