公开(公告)号：JPH11274408A

公开(公告)日：1999-10-08

申请号：JP3293499

申请日：1999-02-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： MUKUTA S FALUKE ,  DAVID E KOTEKKI ,  ROBERT A LITA ,  ROSSNAGEL STEVEN M

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/285 ,  H01L21/822 ,  H01L23/498 ,  H05K1/03 ,  H05K1/16

CPC classification number: H01L23/49894 ,  H01L21/28568 ,  H01L23/49827 ,  H01L23/49866 ,  H01L28/75 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/162

Abstract: PROBLEM TO BE SOLVED: To enhance electronic maintenance and operation characteristic by a method wherein a dielectric member connected to a multilayer ceramic substrate is provided between a lower electrode and an upper electrode containing a noble metal layer, and a barrier layer of TaSiN is provided between a noble metal and a metallic barrier thereunder on a lower surface of the lower electrode.
SOLUTION: An interposer capacitor 13 contains a multilayer ceramic substrate 16, and a thin film capacitor is formed thereon. A thin film structure 34 comprising the capacitor is carried on the multilayer ceramic substrate 16, and has a lower electrode 21 containing a plutinum layer having a TaSiN layer 35 on the lower side. A high K dielectric material 22 separates a platinum electrode 21 from an upper electrode 23 of the capacitor. The upper electrode 23 is covered with a polymer layer 24, and three vias 18, 29, 20 travel from a bottom face of the multilayer ceramic substrate 16 to an upper face thereof in the multilayer ceramic substrate 16, so that substrates are connected to each other and besides an interposer capacitor is connected to the thin film structure.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了通过以下方法提高电子维护和操作特性，其中在下电极和含有贵金属层的上电极之间设置与多层陶瓷基板连接的电介质构件，并且TaSiN的阻挡层设置在 在下电极的下表面上的贵金属和金属屏障。 解决方案：插入电容器13包含多层陶瓷基板16，并且在其上形成薄膜电容器。 包含电容器的薄膜结构34承载在多层陶瓷基板16上，并且具有下侧电极21，该下部电极21在下侧包含具有TaSiN层35的凹凸层。 高K电介质材料22将铂电极21与电容器的上电极23分开。 上部电极23被聚合物层24覆盖，并且三个通路18,29,20从多层陶瓷基板16的底面向多层陶瓷基板16的上表面行进，使得基板与各层 另外，除了中介层电容器连接到薄膜结构之外。

公开(公告)号：JPH10275903A

公开(公告)日：1998-10-13

申请号：JP7674698

申请日：1998-03-25

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  DAVID E KOTEKKI

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method by which a crown capacitor with a Damascene bottom electrode having a larger area than the conventional stack capacitor can be manufactured without using any side-wall spacer. SOLUTION: In a method by which a crown giving structure can be obtained by manufacturing a crown capacitor by using taper etching, chemical and mechanical polishing, and forming a bottom electrode having an increased area, the taper etching is used for forming grooves 30 into an inter-level dielectric layer 20, for example, SiO2 and performed on a contact hole 26 forming a crown-like structure. Then, the grooves 30 and a selective crown are coated with a conductor 32, and the conductor 32 is patterned by the chemical and mechanical polishing.

公开(公告)号：JP2001035841A

公开(公告)日：2001-02-09

申请号：JP2000173200

申请日：2000-06-09

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： AKATSU HIROYUKI ,  DAVID E KOTEKKI ,  SHINGYU JENNIE RYAN ,  SHEN HUA

IPC: H01L21/308 ,  C04B41/53 ,  C04B41/91 ,  H01L21/311 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain production rate which enables commercial use by exposing a ferrodielectric film to mixture of hydrogen chloride and acid and heating the mixture in a specified temperature range. SOLUTION: A substrate having a ferrodielectric film is exposed to solution of hydrogen chloride and acid, and the solution is heated to a temperature between 30 deg.C and 90 deg.C. Wet etching process solution provides BSTO etching rate which is 30 times faster than a usual etching method and it etches titanium nitride and silicon oxide just a little. Etching rate of BSTO increases when a temperature of solution rises toward 70 deg.C, and this fact is important. Although at 50 deg.C, etching rate is about 100 Å/minute, at 70 deg.C, etching rate rises to 600 Å/minute or more. Etching rate of silicon oxide remains low at any temperature.

公开(公告)号：JP2000232210A

公开(公告)日：2000-08-22

申请号：JP2000017633

申请日：2000-01-26

Applicant: IBM

Inventor： LEWIS L SUU ,  DAVID E KOTEKKI ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor which is annealed before formation of a bit line and formed on an active region for the purpose of reducing the size of a memory cell. SOLUTION: This integrated circuit structure is provided with at least a transistor structure, a ferroelectric capacitor 5 of transistor structure, and a conductive circuit 70 located between the transistor structure and the ferroelectric capacitor 50. The ferroelectric capacitor 50 is annealed before the conductive contact 70 is formed.

公开(公告)号：JPH10247722A

公开(公告)日：1998-09-14

申请号：JP849598

申请日：1998-01-20

Applicant: IBM

Inventor： DAVID E KOTEKKI ,  SON V GUEN

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/92

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure which contains high-permittivity insulating material having high memory change and electrostatic capacitance. SOLUTION: A semiconductor device is equipped with a capacitor which contains insulating material in high permittivity and charge hold capacity. The above insulating material is represented by a formula, (A )x (A )2-x (D)d (B )y (B )1-y O4 , where, A and A are cations, B and B are anions, x is so set as to satisfy a condition, 0 and A denote different atoms, y is so set as to satisfy a condition, 0 and B denote different atoms, D denotes dopant which is optionally selected, and the total amount of D is represented by a condition, 0