公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：JPH10275903A

公开(公告)日：1998-10-13

申请号：JP7674698

申请日：1998-03-25

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  DAVID E KOTEKKI

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method by which a crown capacitor with a Damascene bottom electrode having a larger area than the conventional stack capacitor can be manufactured without using any side-wall spacer. SOLUTION: In a method by which a crown giving structure can be obtained by manufacturing a crown capacitor by using taper etching, chemical and mechanical polishing, and forming a bottom electrode having an increased area, the taper etching is used for forming grooves 30 into an inter-level dielectric layer 20, for example, SiO2 and performed on a contact hole 26 forming a crown-like structure. Then, the grooves 30 and a selective crown are coated with a conductor 32, and the conductor 32 is patterned by the chemical and mechanical polishing.

公开(公告)号：JP2005210121A

公开(公告)日：2005-08-04

申请号：JP2005010872

申请日：2005-01-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JEFFREY P GANBINO ,  MOTSIFF WILLIAM T ,  ERIC G WALTON

IPC: H01F41/04 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/822 ,  H01L23/31 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04

CPC classification number: H01L28/10 ,  H01F41/041 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/4902 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To integrate high performance copper inductors with global interconnects, and with either Al bond pads or Cu bond pads. SOLUTION: The integration of high performance copper inductors are conducted wherein a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal + 1 level, with the metal levels interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal + 1 level. The invention provides methods for integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal + 1 wiring. The subject invention uses the dielectric deposition, spacer formation, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：将高性能铜电感器与全局互连以及Al接合焊盘或Cu接合焊盘集成在一起。

解决方案：实现了高性能铜电感器的集成，其中在最后的金属级别形成高的Cu层压螺旋电感器，并且在最后的金属+ 1级别处，金属水平通过棒互连， 与螺旋金属电感器相同的螺旋形状在最后的金属水平和最后的金属+ 1水平。 本发明提供了将厚电感器的形成与最后的金属+ 1布线形成接合焊盘，端子和互连布线的方法。 本发明使用诸如CoWP的钝化金属的电介质沉积，间隔物形成和/或选择性沉积来钝化在最后一个金属层之后形成的Cu电感器。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11297812A

公开(公告)日：1999-10-29

申请号：JP34271998

申请日：1998-12-02

Applicant: IBM ,  TOSHIBA CORP

Inventor： MANDELMAN JACK A ,  MORIKADO MUTSUO ,  HO HERBERT ,  JEFFREY P GANBINO

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To inhibit the formation of a recessed part and to prevent the large change of threshold voltage and off current, by previously removing a nitride liner on the upper part of a side wall with shallow trench element separation. SOLUTION: Resist 17 is etched to the depth of 1000 Å from the surface of a silicon substrate by chemical dry etching(CDE). A silicon nitride liner 16a at the upper part of a shallow trench 14 is removed and whole resist 17a in the shallow trench 14 is removed by CDE. TEOS oxide is embedded in the shallow trench 14, and shallow element separation is formed. A pad nitride film 13 and a pad oxide film 12 on a separated element area are removed, and a gate oxide film and a gate electrode are formed. A source area and a drain area are formed by ion implanting and MOSFET is completed. At the time of removing the pad nitride film 13, a recessed part by the removal of the silicon nitride liner is not formed since the silicon nitride liner is not exposed to a surface.

公开(公告)号：JP2003273235A

公开(公告)日：2003-09-26

申请号：JP2003053740

申请日：2003-02-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MANDELMAN JACK A ,  FILIPPI RONALD G ,  JEFFREY P GANBINO ,  RICHARD A WAKNICK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L21/76897 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with interconnected conductor lines.
SOLUTION: The semiconductor device includes a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines surrounded by an insulator formed on the lower ILD layer are formed on the top surface of the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and the set is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on an upper level. Each of the upper conductor lines has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供配备有互连的导线的半导体器件。 解决方案：半导体器件包括具有形成在衬底上的顶表面的下层间介电层（ILD）层。 在下部ILD层的上表面形成有由下部ILD层形成的绝缘体围绕的多个下部导体线。 一组电阻螺柱中的每一个具有侧壁，下端和上端，并且该组在下端处连接到下导体线的顶部。 在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。 上导线形成在上层。 每个上导体线具有与相应的一个电阻螺柱接触的底表面。 中间ILD层覆盖中间导体，用于将中间导体线与上导体线电绝缘和分离。 版权所有（C）2003，JPO

公开(公告)号：JP2002134631A

公开(公告)日：2002-05-10

申请号：JP2001300150

申请日：2001-09-28

Applicant: IBM

Inventor： ADKISSON JAMES W ,  RAMACHANDORA DEIVAKARUNI ,  JEFFREY P GANBINO ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that comprises an embedded DRAM device and a logic device, and to provide a its manufacturing method. SOLUTION: This device comprises a monocrystal substrate having an almost flat surface, a first surface region on the flat surface having a silicon on insulator region, a second surface region on the flat surface which is a monocrystal bulk region, an embeded logic device which is formed in the silicon on insulator region, an embedded memory device which is formed in the monocrystal bulk region, and a trench in the bulk monocrystal region.

公开(公告)号：JP2001068672A

公开(公告)日：2001-03-16

申请号：JP2000210075

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  JEFFREY P GANBINO ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To obtain an improved structure and a production process of semiconductor device, e.g. MOSFET, in which possibility of thermal shrinkage and permeation of boron are reduced. SOLUTION: A sacrificial oxide layer 1 and a polysilicon/silicon nitride film are deposited sequentially on a substrate 2, an opening is made therein by etching (at the part of 5, 15) and ions are implanted in order to suppress hot carriers 11 thus suppressing punch through 8 between source and drain. After it is filled with a gate insulation film 12, a polysilicon layer 14 and a tungsten layer 15, upper part of an implanted part 18 for extending the source-drain is opened by etching, a spacer 19 is formed therein and contact implantation appropriate to P or N type is carried out. Thereafter, a nitride etch barrier layer 20 is formed, a contact region 21 is opened and filled with a polysilicon layer 22.