公开(公告)号：JP2005117037A

公开(公告)日：2005-04-28

申请号：JP2004283447

申请日：2004-09-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN YUEN H ,  LEWIS L SUU ,  JOSHI RAJIV V ,  WONG ROBERT CHI-FOON

IPC: G11C11/41 ,  G11C11/00 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC classification number: G11C11/412

Abstract: PROBLEM TO BE SOLVED: To provide a method for designing a 6T SRAM cell having greater stability and/or a smaller cell size.
SOLUTION: A 6T SRAM cell has a pair of access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic "0" during access of the cell thereby increasing the stability of the cell, especially for cells during "half select". Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without affecting the stability of the cell during access. And, by decreasing the cell size, the overall design layout area of a chip may also be decreased.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种设计具有更大稳定性和/或更小单元尺寸的6T SRAM单元的方法。 解决方案：6T SRAM单元具有一对存取晶体管（NFET），一对上拉晶体管（PFET）和一对下拉晶体管（NFET），其中存取晶体管具有较高的阈值 电压低于下拉晶体管，这使得SRAM单元在单元访问期间有效地保持逻辑“0”，从而增加了单元的稳定性，特别是对于“半选择”期间的单元。 此外，可以减小下拉晶体管的沟道宽度，从而降低高性能六晶体管SRAM单元的尺寸，而不会影响存取期间单元的稳定性。 而且，通过减小单元尺寸，芯片的总体设计布局面积也可能降低。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：JPH10256394A

公开(公告)日：1998-09-25

申请号：JP3865098

申请日：1998-02-20

Applicant: IBM

Inventor： DONALD C WHEELER ,  LEWIS L SUU ,  MANDELMAN JACK A ,  REBECCA D MI

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a new structure, especially a CMOS structure, decreasing off-state current of a device. SOLUTION: A MOS transistor 70 contains two trench isolation regions 78 adjoining an active region 79. The trench isolation regions 78 is disposed on the opposite sides of the active region 79 so that side walls 80 of each trench acts as an interface for the active region 79, and at least one of the side walls 80 has inclination of 90-150 deg.. The trench isolation regions 78, a source injection region and a drain injection region 78 surround all sides of the active region 79.

公开(公告)号：JP2004193588A

公开(公告)日：2004-07-08

申请号：JP2003389984

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEWIS L SUU ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: G11C11/412 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate. SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a pass gate FET transistor in a silicon layer formed on a flat insulating material and a parallel island, and further forming a pair of vertical pulldown FET transistors having a first common body and a first common source region. The method further forms a pulldown separation space for dividing an upper layer of a pullup and pulldown drain region of a pair of vertical pulldown FET transistor in two by etching through the upper diffusion between cross-linked inverter FET transistors, and the separation space reaches the common boby layer. The method further comprises the steps of forming a pair of vertical pullup FET transistor having a second common body and a second common drain, and connecting the FET transistor so as to form a SRAM cell. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：通过仅使用包括外围（传输）门的垂直MOSFET器件，提供能够同时获得高性能，低功率和小芯片尺寸的SRAM单元设计。 解决方案：一种用于形成SRAM单元器件的方法包括以下步骤：在形成于平坦绝缘材料和平行岛上的硅层中形成栅极FET晶体管，并进一步形成一对垂直下拉FET晶体管，其具有 第一共同体和第一共同源区。 该方法进一步形成一个下拉分离空间，用于通过在交联的反相FET晶体管之间的上部扩散进行蚀刻，将一对垂直下拉式FET晶体管的上拉和下拉漏极区的上层分成两层，分离空间达到 普通boby层。 该方法还包括以下步骤：形成具有第二公共体和第二公共漏极的一对垂直上拉FET晶体管，并连接FET晶体管以形成SRAM单元。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004080036A

公开(公告)日：2004-03-11

申请号：JP2003292574

申请日：2003-08-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  FENG GEORGE C ,  HARPER JAMES M E ,  LEWIS L SUU

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/6659

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving performance in a microelectronic circuit. SOLUTION: A method and a structure for an integrated circuit transistor include a gate conductor having a first conductive material and a second material. The structure has a spacer that is adjacent to the gate conductor and cannot be deformed, and the gap between the gate conductor and the spacer. The first conductive material can be polysilicon, and the second material can be either metal or a polymer. The second material operates as a place holder for the gap. An environmental gas is contained by the gap, and resistance in the gate conductor is reduced. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003229435A

公开(公告)日：2003-08-15

申请号：JP2003003523

申请日：2003-01-09

Applicant: IBM

Inventor： TORISHIA L BREEN ,  CLEVENGER LAWRENCE A ,  LEWIS L SUU ,  WANG LI-KONG ,  WONG KWONG HON

IPC: H01L51/05 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/40

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a flattened polymer transistor, and a structure thereof. SOLUTION: A completely flattened polymer thin film transistor is formed by processing a first portion of a device including a gate, a source, and a body element using a first flattened carrier. The thin film transistor is preferably formed with an organic material. For a gate dielectric a high K polymer can be employed to improve device performance. Then, a partly completed device structure is upside down, and is transferred to a second flattened carrier. A layer of wax or of a photosensitive organic material is deposited and is employed as a tentative bonding agent. A device including a body region is defined with an etching process. A contact to the device is formed with deposition of a conductive material and chemical/mechanical polishing. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000232210A

公开(公告)日：2000-08-22

申请号：JP2000017633

申请日：2000-01-26

Applicant: IBM

Inventor： LEWIS L SUU ,  DAVID E KOTEKKI ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor which is annealed before formation of a bit line and formed on an active region for the purpose of reducing the size of a memory cell. SOLUTION: This integrated circuit structure is provided with at least a transistor structure, a ferroelectric capacitor 5 of transistor structure, and a conductive circuit 70 located between the transistor structure and the ferroelectric capacitor 50. The ferroelectric capacitor 50 is annealed before the conductive contact 70 is formed.

公开(公告)号：JP2000040756A

公开(公告)日：2000-02-08

申请号：JP16743599

申请日：1999-06-14

Applicant: IBM

Inventor： LEWIS L SUU ,  MANDELMAN JACK A

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To design and manufacture a high density flash memory by few number of treatment processes by a method, wherein a polycrystalline silicon spacer is formed on the second side wall having the tilt angle larger than the first sidewall, in such a manner that one side of the polycrystalline silicon spacer is opposed to a word line. SOLUTION: A gate oxide film 3 is formed on a substrate 1, and a gate 4, consisting of n+ or p+ dopant doped polycrystalline silicon, is formed. Then, one sidewall (a second sidewall) 4B of the gate 4 is formed vertically, and the other sidewall (a first side wall) 4A is formed at a tilt angle 45 to 65 degrees. Then, a polycrystalline silicon layer is adhered over the entire surface of a nitride layer and an oxide layer, and the first spacer of polycrystalline silicon and the second spacer which is connected to the first spacer are formed on the part, adjacent to the second sidewall 4B by anisotropic etching in the direction vertical to the surface of the silicon substrate 1. The first and the second spacers are incorporated and function as a sidewall floating gate 7.