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    Inter-si pseudo hydrophobic wafer bonding using solution of interface bonding oxide and hydrophilic si surface
    2.
    发明专利
    Inter-si pseudo hydrophobic wafer bonding using solution of interface bonding oxide and hydrophilic si surface 有权
    界面结合氧化物和疏水性SI表面的解决方案的INTER-SI PSEUDO HYDROPHOBIC WAFER BONDING

    公开(公告)号：JP2006191029A

    公开(公告)日：2006-07-20

    申请号：JP2005363874

    申请日：2005-12-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

    IPC: H01L21/02

    CPC classification number: H01L21/187 ,  H01L21/76251

    Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bonding interface between Si having characteristics equal to that attained by hydrophobic bonding by removing an ultra thin interface oxide remaining after hydrophobic wafer bonding between Si.
    SOLUTION: The interface oxide layer in the order of about 2-3 nm is dissolved and removed by, for example, high temperature annealing at 1,300-1,330°C only for 1-5 hours. The invention is most effectively used if the Si surface of a bonding interface has a different surface orientation as, for example, the Si surface with (100) orientation is bonded to the Si surface with (110) orientation. In more generous modes of this invention, an undesired material arranged on the bonding interface of two silicon-contained semiconductor materials can be removed by a similar annealing process. The surface crystal orientation, fine structure (single crystal, polycrystal, or amorphous), and elements of two silicon-contained semiconductor materials may or may not be identical.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供通过除去Si之间的疏水性晶片接合之后残留的超薄界面氧化物，形成具有与通过疏水接合获得的特性相同的特性的Si之间的结合界面的方法。 解决方案：通过例如1300-133℃的高温退火将约2-3nm量级的界面氧化物层溶解并除去1-5小时。 如果接合界面的Si表面具有不同的表面取向，则本发明是最有效的，因为例如具有（110）取向的具有（100）取向的Si表面结合到Si表面。 在本发明的更宽泛的模式中，可以通过类似的退火工艺去除布置在两个含硅半导体材料的结合界面上的不需要的材料。 表面晶体取向，精细结构（单晶，多晶或非晶）和两个含硅半导体材料的元素可以相同也可以不相同。 版权所有（C）2006，JPO＆NCIPI

    METHOD OF MANUFACTURING REORIENTED Si OF LOW DEFECT DENSITY
    3.
    发明专利
    METHOD OF MANUFACTURING REORIENTED Si OF LOW DEFECT DENSITY 有权
    制造低缺陷密度的重新生成Si的方法

    公开(公告)号：JP2006191028A

    公开(公告)日：2006-07-20

    申请号：JP2005363826

    申请日：2005-12-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DE SOUZA JOEL P ,  FOGEL KEITH E ,  OTT JOHN ALBRECHT ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

    IPC: H01L21/20 ,  H01L21/324

    CPC classification number: H01L21/26506 ,  H01L21/2022

    Abstract: PROBLEM TO BE SOLVED: To provide a method for amorphization/template re-crystallization for changing orientation in the selected region of a silicon, without remaining defect of high density, by preparing an anneal process optimized to remove defects caused by damage due to injection, in a single crystal silicon. SOLUTION: The region of Si having a first crystal orientation is amorphised by iron-implantation, and is re-crystallized into the orientation of a template layer having different orientation, in an amorphising/template re-crystallization (ATR) process. A reoriented Si of low defective density in the process is formed by this method. More specifically, the invention relates to a high temperature annealing condition required for eliminating defects remaining in an Si-contained single crystal semiconductor material formed of the layer whose orientation is identical or different from the original orientation of amorphous layer by amorphising caused by ion-implantation and template re-crystallization. The main factor of that is a thermal process for removing defects remaining after initial re-crystallization annealing, in the temperature range of 1,250-1,330°C for several minutes to several hours. A reoriented Si of low defective density, formed by ATR, is provided as well for use with a hybrid orientation substrate. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供一种用于改变所选择的硅区域中的取向的无定形/模板再结晶的方法，而不存在高密度的缺陷，通过制备优化的消除由于损坏引起的缺陷的退火工艺 注入单晶硅。 解决方案：通过铁注入将具有第一晶体取向的Si区域非晶化，并且在非晶化/模板再结晶（ATR）工艺中，重新结晶成具有不同取向的模板层的取向。 通过该方法形成该方法中的低缺陷密度的重新取向的Si。 更具体地说，本发明涉及一种高温退火条件，用于消除由该离子注入引起的非晶形取向与非晶层的原始取向相同或不同的Si形成的含Si单晶半导体材料残留的缺陷 和模板再结晶。 其主要因素是在初始再结晶退火后，在1,250-133℃的温度范围内去除几分钟至数小时的缺陷的热处理。 还提供了由ATR形成的低缺陷密度的重新取向的Si，以及与混合取向基板一起使用。 版权所有（C）2006，JPO＆NCIPI

    Bipolar junction transistor, and method of forming same
    4.
    发明专利
    Bipolar junction transistor, and method of forming same 有权
    双极接头晶体管及其形成方法

    公开(公告)号：JP2007158333A

    公开(公告)日：2007-06-21

    申请号：JP2006322586

    申请日：2006-11-29

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： WALLNER THOMAS A ,  BEDELL STEPHEN W ,  THOMAS N ADAM ,  DE SOUZA JOEL P

    IPC: H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/737

    CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378

    Abstract: PROBLEM TO BE SOLVED: To provide an improved bipolar junction transistor (BJT) characterized in that the parasitic capacitance has been reduced without reduction in base resistance accompanying the reduction in the parasitic capacitance, and to provide a method of forming the same.
    SOLUTION: The collector region of each BJT is arranged in the surface of a semiconductor substrate and adjacent to a first shallow trench isolation (STI) region. A second STI region is formed while the second STI region extends between the first STI region and the collector region, and undercuts a part of an active base region with an undercut angle of about 90° or less. For example, the second STI region may have a section with a substantially triangular shape with an undercut angle of less than about 90° or a section with a substantially rectangular shape with an undercut angle of about 90°. Such a second STI region can be manufactured using a porous surface part formed in the upper side surface of the collector region.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种改进的双极结型晶体管（BJT），其特征在于，随着寄生电容的减小，寄生电容已经降低而基极电阻没有降低，并且提供了其形成方法。 解决方案：每个BJT的集电极区域布置在半导体衬底的表面中并与第一浅沟槽隔离（STI）区域相邻。 形成第二STI区域，同时第二STI区域在第一STI区域和收集区域之间延伸，并且底切角为约90°或更小的一部分有源基区域。 例如，第二STI区域可以具有具有小于约90°的底切角的基本三角形形状的截面或具有约90°的底切角的基本矩形形状的截面。 可以使用形成在集电区域的上侧表面中的多孔表面部分来制造这样的第二STI区域。 版权所有（C）2007，JPO＆INPIT

    Method of forming integrated semiconductor structure (double simox hybrid orientation technic (hot) substrate)
    5.
    发明专利
    Method of forming integrated semiconductor structure (double simox hybrid orientation technic (hot) substrate) 有权
    形成集成半导体结构的方法（双SIMOX混合定向技术（热）衬底）

    公开(公告)号：JP2006041526A

    公开(公告)日：2006-02-09

    申请号：JP2005213971

    申请日：2005-07-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KEVIN K CHAN ,  DE SOUZA JOEL P ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

    IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a device on a crystal of orientation which brings about optimal performance by providing separation by an oxygen implantation (SIMOX) method for the formation of a flat hybrid orientation semiconductor on insulator (SOI) substrate having a crystal of different orientation. SOLUTION: A method comprises steps of: selecting a substrate having a lower semiconductor layer having first crystal orientation separated from an upper semiconductor layer having second crystal orientation by a thin insulating layer; replacing the upper semiconductor layer of a selected region with epitaxial growth semiconductor having the first crystal orientation; (i) forming a padding insulating region in an epitaxial growth semiconductor material and (ii) thickening an insulating layer under the upper semiconductor layer using ion implantation and annealing methods; and forming a hybrid orientation substrate in which two semiconductor materials of different crystal orientation have substantially identical thickness and are arranged on the common padding insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种通过提供通过氧注入（SIMOX）方法分离以形成绝缘体上的平坦混合取向半导体（SOI）的方向来制造取向晶体的装置的方法，该方法产生最佳性能 ）衬底具有不同取向的晶体。 解决方案：一种方法包括以下步骤：通过薄绝缘层，选择具有从具有第二晶体取向的上半导体层分离的具有第一晶体取向的下半导体层的衬底; 用具有第一晶体取向的外延生长半导体代替所选区域的上半导体层; （i）在外延生长半导体材料中形成填充绝缘区域，和（ii）使用离子注入和退火方法使上半导体层下方的绝缘层增厚; 以及形成混合取向基板，其中两个不同晶体取向的半导体材料具有基本上相同的厚度并且布置在公共衬垫绝缘层上。 版权所有（C）2006，JPO＆NCIPI

    Kontakt mit geringem Widerstand für Halbleiter-Einheiten
    9.
    发明专利
    Kontakt mit geringem Widerstand für Halbleiter-Einheiten 未知

    公开(公告)号：DE102016104446B4

    公开(公告)日：2020-08-06

    申请号：DE102016104446

    申请日：2016-03-11

    Applicant: IBM

    Inventor： DE SOUZA JOEL P ,  FOGEL KEITH E ,  KIM JEEHWAN ,  SADANA DEVENDRA K ,  WACASER BRENT A

    IPC: H01L29/49 ,  H01L23/485 ,  H01L23/52 ,  H01L29/20 ,  H01L29/772

    Abstract: Halbleiter-Einheit, die aufweist:ein Substrat (42);eine p-dotierte Schicht (44), die ein dotiertes III-V-Material beinhaltet, auf dem Substrat;ein Material vom n-Typ (46), das auf oder in der p-dotierten Schicht (44) ausgebildet ist, wobei das Material vom n-Typ ein dotiertes III-V-Material beinhaltet; undeinen Kontakt (66), der auf dem Material vom n-Typ (46) ausgebildet ist und eine Zwischenschicht (48), die aus ZnO gebildet ist, sowie einen Teilbereich (51) aus Aluminium beinhaltet, der in direktem Kontakt zu dem ZnO der Zwischenschicht (48) ausgebildet ist, um eine elektronische Einheit zu bilden, wobei die Zwischenschicht (48) und der Teilbereich (51) aus Aluminium zusammen strukturiert werden, um den Kontakt zu bilden.

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