公开(公告)号：EP1479103A4

公开(公告)日：2005-02-09

申请号：EP03731957

申请日：2003-01-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHU JACK O ,  FOGEL KEITH E ,  KOESTER STEPHEN J ,  SADANA DEVENDRA K ,  OTT JOHN ALBRECHT

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L21/331

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

Abstract translation: 提供了一种形成薄的，高品质的弛豫SiGe绝缘体上的基板材料的方法，其首先包括形成第一单晶Si层的表面上的SiGe或纯Ge层，其存在的顶上即耐阻挡层 到Ge的扩散。 OPTIONALLY形成在SiGe或纯Ge层中的Si间隙层，并随后在其允许的Ge的相互扩散在整个第一单晶Si层的温度下加热的各种层，任选的Si盖和SiGe或纯Ge层，从而形成 基本松弛，单晶SiGe层在阻挡层上。 额外的SiGe再生长和/或形成的应变外延Si层的可遵循上述步骤。 上SiGe绝缘体基板材料以及包含结构至少在SiGe绝缘体上的基板材料，因此是在盘游离缺失。

公开(公告)号：EP1554915A4

公开(公告)日：2008-08-20

申请号：EP03726799

申请日：2003-05-13

Applicant: IBM

Inventor： HOUGHAM GARETH G ,  FOGEL KEITH E ,  LAURO PAUL A ,  ZINTER JOSEPH

IPC: H01R13/24 ,  H01R43/00 ,  H05K3/40 ,  H05K3/42 ,  H05K7/10

CPC classification number: H01R13/2414 ,  H01R12/7082 ,  H01R12/714 ,  H01R43/007 ,  H05K3/4007 ,  H05K3/42 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0959 ,  H05K2201/10378 ,  Y10S439/931 ,  Y10T442/109 ,  Y10T442/172

Abstract: Methods for fabricating Land Grid Array (LGA) interposer contacts that are both conducting and elastic.Also provided are LGA interposer contacts as produced by the inventive methods. Provided is LGA type which utilizes a pure unfilled elastomer button core that is covered with an electrically-conductive material that is continuous from the top surface to the bottom surface of the button structure. In order to obviate the disadvantages and drawbacks which are presently encountered in the technology pertaining to the fabrication and structure of land grid arrays using electrically-conductive interposer contacts, there isprovided both methods and structure for molding elastomer buttons into premetallized LGA carrier sheets,and wherein the non-conductive elastomer buttons are surface-metallized in order to convert them intoconductive electrical contacts.

公开(公告)号：EP1886342A4

公开(公告)日：2011-06-15

申请号：EP06770646

申请日：2006-05-18

Applicant: IBM

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

公开(公告)号：WO2004109776A3

公开(公告)日：2005-05-19

申请号：PCT/US2004016903

申请日：2004-05-28

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

Abstract translation: 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

公开(公告)号：JP2006191028A

公开(公告)日：2006-07-20

申请号：JP2005363826

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  FOGEL KEITH E ,  OTT JOHN ALBRECHT ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/324

CPC classification number: H01L21/26506 ,  H01L21/2022

Abstract: PROBLEM TO BE SOLVED: To provide a method for amorphization/template re-crystallization for changing orientation in the selected region of a silicon, without remaining defect of high density, by preparing an anneal process optimized to remove defects caused by damage due to injection, in a single crystal silicon. SOLUTION: The region of Si having a first crystal orientation is amorphised by iron-implantation, and is re-crystallized into the orientation of a template layer having different orientation, in an amorphising/template re-crystallization (ATR) process. A reoriented Si of low defective density in the process is formed by this method. More specifically, the invention relates to a high temperature annealing condition required for eliminating defects remaining in an Si-contained single crystal semiconductor material formed of the layer whose orientation is identical or different from the original orientation of amorphous layer by amorphising caused by ion-implantation and template re-crystallization. The main factor of that is a thermal process for removing defects remaining after initial re-crystallization annealing, in the temperature range of 1,250-1,330°C for several minutes to several hours. A reoriented Si of low defective density, formed by ATR, is provided as well for use with a hybrid orientation substrate. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种用于改变所选择的硅区域中的取向的无定形/模板再结晶的方法，而不存在高密度的缺陷，通过制备优化的消除由于损坏引起的缺陷的退火工艺 注入单晶硅。 解决方案：通过铁注入将具有第一晶体取向的Si区域非晶化，并且在非晶化/模板再结晶（ATR）工艺中，重新结晶成具有不同取向的模板层的取向。 通过该方法形成该方法中的低缺陷密度的重新取向的Si。 更具体地说，本发明涉及一种高温退火条件，用于消除由该离子注入引起的非晶形取向与非晶层的原始取向相同或不同的Si形成的含Si单晶半导体材料残留的缺陷 和模板再结晶。 其主要因素是在初始再结晶退火后，在1,250-133℃的温度范围内去除几分钟至数小时的缺陷的热处理。 还提供了由ATR形成的低缺陷密度的重新取向的Si，以及与混合取向基板一起使用。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005294827A

公开(公告)日：2005-10-20

申请号：JP2005085734

申请日：2005-03-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FOGEL KEITH E ,  BALARAM GHOSAL ,  SUNG K KANG ,  STEPHEN KILPATRICK ,  PAUL A LAURO ,  HENRY A NYE III ,  DA-YUAN SHIH ,  DONNA S ZUPANSKI-NIELSEN

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/485 ,  H05K3/34

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a ball-limiting metallurgy (BLM) structure for flip chip connection, which is suitable for use together with a lead-free solder. SOLUTION: An interconnection structure suitable for flip chip connection of microelectronic device chips to packages has a two-, three- or four-layer ball-limiting composition. The composition includes an adhesion/reaction barrier layer and has a solder wettable layer reactive with components of a tin-containing lead-free solder. The solderable layer can be therefore totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead-free solder during soldering. One or more lead-free solder balls are selectively positioned on the solder wettable layer. The lead-free solder balls comprise tin as a main component and one or more alloying components. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供适合与无铅焊料一起使用的倒装芯片连接用的限界冶金（BLM）结构。 解决方案：适用于微电子器件芯片与封装的倒装芯片连接的互连结构具有二，三或四层球限制组合物。 该组合物包括粘合/反应阻挡层，并且具有与含锡无铅焊料的组分反应的焊料可湿性层。 因此可焊接层在焊接时可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。 一个或多个无铅焊球选择性地定位在焊料可润湿层上。 无铅焊球包括锡作为主要成分和一种或多种合金成分。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004363592A

公开(公告)日：2004-12-24

申请号：JP2004158994

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHAHIDI GHAVAM G ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  FOGEL KEITH E

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a substantially relaxed high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion. SOLUTION: In order to form an injection rich area in a Si-containing substrate, ions are injected into Si-containing substrate at the beginning. The inplanted-ion rich region has sufficient ion concentration so that a barrier layer to disturb Ge diffusion is formed during annealing at a high temperature. Next, Ge-containing layer is formed on a surface of the Si-containing substrate, and then a heating process is performed at a temperature that enables the formation of a barrier layer, and the Ge interdiffusion. This allows a substantially relaxed single-crystal SiGe layer to be formed on the barrier layer. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2005094006A

公开(公告)日：2005-04-07

申请号：JP2004266302

申请日：2004-09-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  NARASIMHA SHREESH

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L27/12

CPC classification number: H01L21/2022 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide an improving method of the quality of a defective semiconductor crystal in the vicinity of the surface thereof.
SOLUTION: A method where amorphization step and subsequent thermal treatment step are executed on the defective semiconductor crystal material is provided. In the amorphization step, a region including the surface area of the defective semiconductor crystal material is partially or completely amorphized. Next, the thermal treatment step is executed to recrystallize the amorphized area of the defective semiconductor crystal material. Recrystallization is achieved, by re-growing the solid phase crystal from the amorphized area of the defective semiconductor crystal material.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在其表面附近的缺陷半导体晶体的质量的改进方法。 解决方案：提供了对缺陷半导体晶体材料执行非晶化步骤和随后的热处理步骤的方法。 在非晶化步骤中，包含缺陷半导体晶体材料的表面积的区域部分或完全非晶化。 接下来，进行热处理步骤，使缺陷半导体晶体材料的非晶化区域重结晶。 通过从有缺陷的半导体晶体材料的非晶化区域重新生长固相晶体来实现重结晶。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005026681A

公开(公告)日：2005-01-27

申请号：JP2004183839

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an SiGe-on-insulator substrate material substantially relaxed, of high quality, and capable of being used as a template for strained-silicon. SOLUTION: The SOI substrate having an ultra-thin top Si layer is used as the template for compressive strain SiGe growth. When an SiGe layer is relaxed at an enough temperature, the property of its dislocation movement is such that strain release defect moves down into the thin Si layer when an embedded oxide shows semi-viscosity behavior. The thin Si layer is consumed by oxidation of an interface of the thin Si with the embedded oxide. This can be performed by using inner oxidation at a high temperature. Therefore, the role of the original thin Si layer is to use the inner oxidation and subsequently to act as a sacrificial defective sink capable of being consumed during an SiGe alloy being relaxed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造绝缘体上绝缘体衬底材料的方法，其基本上是松弛的，高质量的，并且能够用作应变硅的模板。 解决方案：使用具有超薄顶部Si层的SOI衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下松弛时，其位错运动的性质使得当嵌入的氧化物显示半粘度行为时，应变释放缺陷向下移动到薄的Si层中。 薄的Si层被薄的Si与嵌入的氧化物的界面的氧化所消耗。 这可以通过在高温下使用内部氧化来进行。 因此，原始薄Si层的作用是使用内部氧化，随后作为在SiGe合金松弛期间能够消耗的牺牲缺陷槽。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004040122A

公开(公告)日：2004-02-05

申请号：JP2003274987

申请日：2003-07-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  DEVENDORA K SADANA

IPC: H01L29/161 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a relaxed SiGe-on-insulator substrate having improved relaxation, comparatively low defect density, and improved surface quality.
SOLUTION: The method includes a step for forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlay barrier layer having resistance to Ge diffusion. Next, ions are implanted into the structure, the ions forming defects by which mechanical decoupling is achieved at the interface or vicinity of the interface; then a heating step is performed to the structure including the implanted ions, by which mutual diffusion of Ge through the first single crystal Si layer and SiGe layer is achieved; thereby a SiGe layer that is substantially relaxed single crystal and homogenous is formed on the barrier layer. A SiGe-on-insulator having improved properties and a heterostructure including it are also provided.
COPYRIGHT: (C)2004,JPO