公开(公告)号：DE2333381A1

公开(公告)日：1974-01-24

申请号：DE2333381

申请日：1973-06-30

Applicant: IBM

Inventor： DONOFRIO NICHOLAS MICHAEL ,  KEMERER DOUGLAS WAYNE

IPC: G11C11/41 ,  G11C11/414 ,  G11C11/416 ,  G11C7/00

Abstract: The specification describes a sense amplifier/bit driver circuit having an active bit/sense line pull-up circuit. The active pull-up circuit is shown substantially as two transistors connected between the bit driver circuit and the bit/sense lines. A normal write operation is performed by pulling one bit/sense line to a down level (ground) potential and retaining the other bit/sense line at an up level (positive) voltage. Immediately after the write operation, recovery time is required to bring the down level bit/sense line back to the up level for subsequent read/write operations. The pull-up circuit described in the specification is turned on to perform this function and maintained off in order not to interfere with other operations.

公开(公告)号：DE2359150A1

公开(公告)日：1974-07-11

申请号：DE2359150

申请日：1973-11-28

Applicant: IBM

Inventor： DONOFRIO NICHOLAS MICHAEL ,  KEMERER DOUGLAS WAYNE ,  ESSEX JUNCTION VT ,  RAYMOND JUN JOHN

IPC: H03M7/02 ,  H03K19/096 ,  H03K19/08

Abstract: Disclosed is a true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals. A first portion of the true complement generator is a gated inverter circuit generating a complement output. A second portion of the true complement generator is a gated driver circuit generating a true output. The true and complement phases of the input signal appear at the respective output nodes during the occurrence of a first timing signal, while both output nodes are held to the same level during the occurrence of a second timing signal.

公开(公告)号：DE2331440A1

公开(公告)日：1974-01-17

申请号：DE2331440

申请日：1973-06-20

Applicant: IBM

Inventor： SONODA GEORGE ,  WADE WILLIAM THOMAS ,  POUGHKEEPSIE N Y ,  DESIMONE ROY RALPH ,  DONOFRIO NICHOLAS MICHAEL ,  LINTON RICHARD HENRY

IPC: G11C11/412 ,  G11C8/04 ,  G11C8/16 ,  G11C11/402 ,  G11C11/406 ,  G11C7/00

Abstract: An electronic data storage which operates as a DC stable storage array, but retains the advantages of an AC stable storage cell circuit. The AC stable storage cells are regenerated at a frequency asynchronous with respect to the storage cycle time. Gating means inhibit the regenerating signals when the system desires access, thereby permitting the storage cells to be accessed for information at any time in a completely random access mode.

公开(公告)号：DE2325871A1

公开(公告)日：1974-01-17

申请号：DE2325871

申请日：1973-07-14

Applicant: IBM

Inventor： BENANTE JOSEPH FREDERICK ,  DONOFRIO NICHOLAS MICHAEL

IPC: G11C11/412 ,  G01R31/27 ,  G01R31/28 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  G11C7/00

Abstract: The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.