公开(公告)号：JP2008004939A

公开(公告)日：2008-01-10

申请号：JP2007160933

申请日：2007-06-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HE ZHONG-XIANG ,  ESHUN EBENEZER E ,  DOUGLAS D COOLBAUGH ,  RASSEL ROBERT MARK

IPC: H01L21/822 ,  H01L21/3205 ,  H01L23/52 ,  H01L27/04

CPC classification number: H01L28/60

Abstract: PROBLEM TO BE SOLVED: To provide an MIM capacitor device and a method for manufacturing it. SOLUTION: This device includes: an upper plate which comprises one or more conductive layers and has an upper surface, a lower surface and a side wall; a spreader plate which comprises one or more conductive layers and has an upper surface, a lower surface and a side wall; and a dielectric block which comprises one or more dielectric layers and has an upper surface, a lower surface and a side wall. The upper surface of the dielectric block is physically in contact with the lower surface of the upper plate. The lower surface of the dielectric block is above the upper surface of the spreader plate. The side wall of the upper plate and the dielectric block is essentially coplanar. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种MIM电容器装置及其制造方法。 解决方案：该装置包括：上板，其包括一个或多个导电层，并具有上表面，下表面和侧壁; 包括一个或多个导电层并具有上表面，下表面和侧壁的扩展板; 以及包括一个或多个电介质层并具有上表面，下表面和侧壁的介电块。 介质块的上表面物理地与上板的下表面接触。 介质块的下表面在扩展板的上表面之上。 上板和介质块的侧壁基本上是共面的。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：MY124964A

公开(公告)日：2006-07-31

申请号：MYPI20004901

申请日：2000-10-18

Applicant: IBM

Inventor： DOUGLAS D COOLBAUGH ,  DAVID L HARAME ,  JAMES S DUNN ,  PETER J GEISS ,  PETER B GRAY ,  KATHRYN T SCHONENBERG ,  STEPHEN A ST ONGE ,  SESHADRI SUBBANNA

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A METHOD FOR FORMING A BICMOS INTEGRATED CIRCUIT IS PROVIDED WHICH COMPRISES THE STEPS OF: (A) FORMING A FIRST PORTION OF A BIPOLAR DEVICE IN FIRST REGIONS OF A SUBSTRATE; (B) FORMING A FIRST PROTECTIVE LAYER OVER SAID FIRST REGIONS TO PROTECT SAID FIRST PORTION OF SAID BIPOLAR DEVICES: (C) FORMING FIELD EFFECT TRANSISTOR DEVICES IN SECOND REGIONS OF SAID SUBSTRATE; (D) FORMING A SECOND PROTECTIVE LAYER OVER SAID SECOND REGIONS OF SAID SUBSTRATE TO PROTECT SAID FIELD EFFECT TRANSISTOR DEVICES; (E) REMOVING SAID FIRST PROTECTIVE LAYER; (F) FORMING A SECOND PORTION OF SAID BIPOLAR DEVICES IN SAID FIRST REGIONS OF SAID SUBSTRATE; AND (G) REMOVING SAID SECOND PROTECTIVE LAYER.(FIG 1)

公开(公告)号：MY133800A

公开(公告)日：2007-11-30

申请号：MYPI20011502

申请日：2001-03-29

Applicant: IBM

Inventor： DOUGLAS D COOLBAUGH ,  JAMES STUART DUNN ,  STEPHEN ARTHUR ST ONGE

IPC: H01L27/04 ,  H01L27/108 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/92 ,  H01L29/94

Abstract: A STACKED POLY-POLY/MOS CAPACITOR USEFUL AS A COMPONENT IN A BICMOS DEVICE COMPRISING A SEMICONDUCTOR SUBSTRATE HAVING A REGION OF A FIRST CONDUCTIVITY-TYPE FORMED IN A SURFACE THEREOF; A GAT E OXIDE FORMED ON SAID SEMICONDUCTOR SUBSTRATE OVERLYING SAID REGION OF FIRST CONDUCTIVITYTYPE; A FIRST POLYSILICON LAYER FORMED ON AT LEAST SAID GATE OXIDE LAYER, SAID FIRST POLYSILICON LAYER BEING DOPED WITH AN N OR P-TYPE DOPANT; A DIELECTRIC LAYER FORMED ON SAID FIRST POLYSILICON LAYER; AND A SECOND POLYSILICON LAYER FORMED ON SAID DIELECTRIC LAYER ; SAID SECOND POLYSILICON LAYER BEING DOPED WITH THE SAME OR DIFFERENT DOPANT AS THE FIRST POLYSILICON LAYER.@@FIGURE 4

公开(公告)号：MY134124A

公开(公告)日：2007-11-30

申请号：MYPI20021676

申请日：2002-05-09

Applicant: IBM

Inventor： DOUGLAS D COOLBAUGH ,  KATHRYN T SCHONENBERG

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/10 ,  H01L29/737

Abstract: A METHOD FOR IMPROVING THE SiGe BIPOLAR YIELD AS WELL AS FABRICATING A SiGe HETEROJUNCTION BIPOLAR TRANSISTOR IS PROVIDED. THE INVENTIVE METHOD INCLUDES ION-IMPLANTING CARBON, C, INTO AT ONE OF THE FOLLOWING REGIONS OF THE DEVICE; THE COLLECTOR REGION, THE SUB-COLLECTOR REGION, THE EXTRINSIC BASE REGIONS, AND THE COLLECT0R-BASE JUNCTION REGION. IN A PREFERRED EMBODIMENT EACH OF THE AFORESAID REGIONS INCLUDE C IMPLANTS.@@@@FIGURE 1

公开(公告)号：SG99316A1

公开(公告)日：2003-10-27

申请号：SG200004756

申请日：2000-08-22

Applicant: IBM

Inventor： DOUGLAS D COOLBAUGH ,  DAVID L HARAME

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/822 ,  H01L29/70 ,  H01L29/94 ,  H01L27/04 ,  H01L21/324 ,  H01L21/22 ,  H01L29/78

Abstract: A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.