公开(公告)号：JP2001185634A

公开(公告)日：2001-07-06

申请号：JP2000340616

申请日：2000-11-08

Applicant: IBM

Inventor： DOUGLAS D KUURUBAAGU ,  JAMES S DAN ,  PETER J JEAYES ,  PETER B GRAY ,  DAVID L HALLAM ,  CATHRIN T SHOONENBAAGU ,  STEPHEN A SAINT ON ,  SESHADORI SAVANA

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiMOS integrated circuit in which an FET and a bipolar element are formed on the same substrate. SOLUTION: The method for forming a BiMOS integrated circuit comprises a step for forming a collector at the first part of a bipolar element in the first region of a substrate, a step for protecting the first part of the bipolar element by forming a first protective layer on the first region, a step for forming a field effect transistor element in the second region of the substrate, a step for protecting the field effect transistor element by forming a second protective layer on the second region of the substrate, a step for removing the first protective layer, a step for forming a base and an emitter at the second part of the bipolar element, and a step for removing the second protective layer.

公开(公告)号：MY124964A

公开(公告)日：2006-07-31

申请号：MYPI20004901

申请日：2000-10-18

Applicant: IBM

Inventor： DOUGLAS D COOLBAUGH ,  DAVID L HARAME ,  JAMES S DUNN ,  PETER J GEISS ,  PETER B GRAY ,  KATHRYN T SCHONENBERG ,  STEPHEN A ST ONGE ,  SESHADRI SUBBANNA

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A METHOD FOR FORMING A BICMOS INTEGRATED CIRCUIT IS PROVIDED WHICH COMPRISES THE STEPS OF: (A) FORMING A FIRST PORTION OF A BIPOLAR DEVICE IN FIRST REGIONS OF A SUBSTRATE; (B) FORMING A FIRST PROTECTIVE LAYER OVER SAID FIRST REGIONS TO PROTECT SAID FIRST PORTION OF SAID BIPOLAR DEVICES: (C) FORMING FIELD EFFECT TRANSISTOR DEVICES IN SECOND REGIONS OF SAID SUBSTRATE; (D) FORMING A SECOND PROTECTIVE LAYER OVER SAID SECOND REGIONS OF SAID SUBSTRATE TO PROTECT SAID FIELD EFFECT TRANSISTOR DEVICES; (E) REMOVING SAID FIRST PROTECTIVE LAYER; (F) FORMING A SECOND PORTION OF SAID BIPOLAR DEVICES IN SAID FIRST REGIONS OF SAID SUBSTRATE; AND (G) REMOVING SAID SECOND PROTECTIVE LAYER.(FIG 1)