公开(公告)号：HK1040569A1

公开(公告)日：2002-06-14

申请号：HK02101938

申请日：2002-03-13

Applicant: IBM

Inventor： ALCOE DAVID J ,  DOWNES FRANCIS J JR ,  JONES GERALD W ,  KRESGE JOHN S ,  TYTRAN-PALOMAKI CHERYL L

IPC: H01L23/498 ,  H05K3/46 ,  H01L ,  H05K

Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.