公开(公告)号：DE10120868A1

公开(公告)日：2001-12-20

申请号：DE10120868

申请日：2001-04-27

Applicant: IBM

Inventor： ALCOE DAVID J ,  DOWNES FRANCIS J ,  JONES GERALD W ,  KRESGE JOHN S ,  TYTRAN-PALOMAKI CHERYL L

IPC: H01L23/498 ,  H05K3/46 ,  H05K3/42

Abstract: Connecting structure comprises a support material (100), a metallic through-hole arranged in the carrier material; a re-distributing layer on a first an a second surface of the carrier material; and a through-contact within the re-distributing layer and selectively arranged above the through-hole and electrically connected to it. Preferred Features: The support material comprises: a base surface (112); a first dielectric material layer (114); a first pair of first signal surfaces (116); a second dielectric material layer (118); a first pair of conducting surfaces (120); a third dielectric material layer (122); a second pair of second signal surfaces (124); a fourth dielectric material layer (126); and a second pair of second conducting surfaces (128). The base surface is a layer of copper-invar-copper. The first and second signal surfaces are impedance-controlled switching circuit layers.

公开(公告)号：HK1040569A1

公开(公告)日：2002-06-14

申请号：HK02101938

申请日：2002-03-13

Applicant: IBM

Inventor： ALCOE DAVID J ,  DOWNES FRANCIS J JR ,  JONES GERALD W ,  KRESGE JOHN S ,  TYTRAN-PALOMAKI CHERYL L

IPC: H01L23/498 ,  H05K3/46 ,  H01L ,  H05K

Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.