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    SIGNAL DELAY CIRCUIT, PROGRAMMABLE DELAY ELEMENT, SIGNAL DELAY METHOD AND PROGRAMMABLE DELAY CIRCUIT
    1.
    发明专利
    SIGNAL DELAY CIRCUIT, PROGRAMMABLE DELAY ELEMENT, SIGNAL DELAY METHOD AND PROGRAMMABLE DELAY CIRCUIT 失效

    公开(公告)号：JP2000269794A

    公开(公告)日：2000-09-29

    申请号：JP2000049573

    申请日：2000-02-25

    Applicant: IBM

    Inventor： ALBERT MANHII CHUU ,  DANIEL MARK DROPS ,  FERRAIOLO FRANK D ,  KEVIN CHARLES GOWER ,  ROGER PAUL GREGOR

    IPC: G06F5/06 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable delay element circuit that is used for a high-performance computer system. SOLUTION: A programmable delay element 100 is provided with a precise delay element 200 having a fractional delay unit. The precise delay element 200 is provided with a precise delay circuit having a plurality of selective delay paths. The precise delay element 200 is electrically connected to a data terminal used to receive and delay an input signal. A control circuit is electrically connected to the precise delay element 200 to select a delay path for the input signal. Furthermore, the precise delay element 200 is electrically coupled to a rough delay circuit 115 provided with a plurality of selective delay blocks adopting a repetitive configuration. The control circuit is electrically coupled to the selective delay paths of the precise delay element 200 and the rough delay circuit 115, so as to select a precise delay or a rough delay or both the precise delay and the rough delay.

    Interface between self-repair chips
    3.
    发明专利
    Interface between self-repair chips 审中-公开
    自我修复界面

    公开(公告)号：JP2004220598A

    公开(公告)日：2004-08-05

    申请号：JP2003431365

    申请日：2003-12-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BECKER WIREN DALE ,  DREPS DANIEL MARK ,  FERRAIOLO FRANK D ,  HARIDASS ANAND ,  REESE ROBERT JAMES

    IPC: G06F13/00 ,  G06F11/26 ,  H01L21/66

    CPC classification number: H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for managing a set of signal paths of a chip and to provide a computer instruction. SOLUTION: A defective signal path among the set of signal paths of the chip is detected. A route of a signal is specified again via the set of signal paths in response to detection of the defective signal path, the defective signal path is eliminated from the set of signal paths and the signal is transmitted by using the remaining data signal path of the set of signal paths and using an excess signal path. In addition, the chip is a data source, a test pattern is generated by the data source, the test pattern is transmitted to a data destination by using the set of signal paths, the received pattern is compared with expected data at the data destination and whether or not the defective signal path exists is determined by utilizing this comparison result. COPYRIGHT: (C)2004,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于管理芯片的一组信号路径并提供计算机指令的方法和装置。 解决方案：检测芯片组的信号路径中的有缺陷的信号路径。 响应于缺陷信号路径的检测，再次通过信号路径集合指定信号的路线，从信号路径组中消除了缺陷信号路径，并且通过使用信号路径的剩余数据信号路径来发送信号 一组信号路径并使用多余的信号路径。 另外，芯片是数据源，由数据源产生测试模式，通过使用该组信号路径将测试模式发送到数据目的地，将接收的模式与数据目的地的预期数据进行比较， 通过利用该比较结果确定存在缺陷信号路径。 版权所有（C）2004，JPO＆NCIPI

    System and method of low latency data tranfer between clock domains operated in various synchronization modes
    5.
    发明专利
    System and method of low latency data tranfer between clock domains operated in various synchronization modes 未知

    公开(公告)号：GB2513529A

    公开(公告)日：2014-11-05

    申请号：GB201220534

    申请日：2012-11-15

    Applicant: IBM

    Inventor： HARRER HUBERT ,  DREPS DANIEL M ,  FERRAIOLO FRANK D ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

    IPC: G06F1/12 ,  G06F1/08 ,  G06F13/40

    Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency, the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

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