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公开(公告)号：DE3883528T2
公开(公告)日：1994-03-17
申请号：DE3883528
申请日：1988-06-16
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE LES JARDINS DE CESS , SAINT-GEORGES ERIC
Abstract: This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6.
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Patent Agency Ranking
公开(公告)号：DE68919696T2
公开(公告)日：1995-05-24
申请号：DE68919696
申请日：1989-09-26
Applicant: IBM
Inventor： CALVIGNAC JEAN CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 ans 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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公开(公告)号：CA2018068C
公开(公告)日：1994-09-06
申请号：CA2018068
申请日：1990-06-01
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 and 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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4.发明专利
公开(公告)号：CA1313412C
公开(公告)日：1993-02-02
申请号：CA597345
申请日：1989-04-20
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE , SAINT-GEORGES ERIC
Abstract: FR 9 88 005 PARALLEL PROCESSING METHOD AND DEVICE FOR RECEIVING AND TRANSMITTING HDLC SDLC BIT STREAMS This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6. (Figure 2)
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公开(公告)号：DE68919696D1
公开(公告)日：1995-01-12
申请号：DE68919696
申请日：1989-09-26
Applicant: IBM
Inventor： CALVIGNAC JEAN CALVIGNAC JEAN , FERAUD JACQUES , LIPS JEAN-PIERRE , NAUDIN BERNARD , SAINT-GEORGES ERIC
Abstract: The subject distribution mechanism is used in a communication system comprising a plurality of interfaces, (10, 11 ans 12) with each interface connected to at least one user and able to receive and transmit information to said user(s) through information carrying means. It allows communications to be established between users selected by a central control unit (7) in a programmable way. The distribution mechanism comprises: in each interface, scheduling means responsive to a common timing signal having a period T, to divide the period into n slot periods having a slot number, n being the number of users connected to that interface to which the maximum number of users are connected, a configuration table (18) comprising n locations, each location assigned to a slot period, the central control unit writing in each location communication control information, said table being addressed by the slot numbers generated by the scheduling means to read and make available, the communication control information, distribution buffer means (20) comprising at least a first and a second part, each part having n addressable locations, addressed by means of addressing means responsive to the communication control information provided by the configuration table during each slot period to cause each interface involved in the to be established communications during that slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot number generated by the scheduling means.
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公开(公告)号：DE3883528D1
公开(公告)日：1993-09-30
申请号：DE3883528
申请日：1988-06-16
Applicant: IBM
Inventor： CALVIGNAC JEAN , FERAUD JACQUES , NAUDIN BERNARD , PIN CLAUDE LES JARDINS DE CESS , SAINT-GEORGES ERIC
Abstract: This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6.
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