公开(公告)号：JP2000353089A

公开(公告)日：2000-12-19

申请号：JP2000162612

申请日：2000-05-31

Applicant: IBM

Inventor： BENAYOUN ALAIN ,  LE PENNEC JEAN-FRANCOIS ,  PIN CLAUDE ,  MICHEL PATRICK

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318

Abstract: PROBLEM TO BE SOLVED: To provide a hardware device which better responds to the necessity of each program, can use a simple instruction when necessary and processes an instruction set that can use more complicated instruction than adaptable to a basic instruction sequence used most frequently. SOLUTION: This device is a hardware device which processes in parallel a decided instruction out of a programmable instruction set that shares a format and has an instruction code field defining an execution step of an instruction corresponding to execution of a microinstruction. In this case, judgment blocks (12 to 20) each of which is associated with a specific instruction of a programmable instruction set and only one of which is selected by a decision instruction in order to define a specific microinstruction to be processed for executing a decided instruction, activation blocks (22 to 30) each of which is associated with the judgment blocks, executes the specific microinstruction and only one of which associated with the selected judgment block is activated and executes the specific microinstruction, and a microinstruction selection block 46 which is connected to each of the activation blocks and selects the specific microinstruction to be executed.

公开(公告)号：FR2803672B1

公开(公告)日：2006-09-22

申请号：FR0014658

申请日：2000-11-14

Applicant: IBM

Inventor： BENAYOUN ALAIN ,  MICHEL PATRICK ,  LE PENNEC JEAN FRANCOIS ,  PIN CLAUDE

IPC: G06F13/38 ,  G06F13/12

Abstract: System for transferring a data file from a web server to a user workstation through a network and reciprocally, the user workstation including a hard disk ( 205 ) for storing the data file being transferred over a SCSI bus ( 208 ). The user workstation includes a dual-port memory ( 304 ) for storing temporarily the data file, a network logic unit ( 302 ) interconnected between the network and the input port of the dual-port memory for receiving the data file from the network and transmitting it to the dual-port memory, and a SCSI logic unit ( 303 ) interconnected between the output port of the dual-port memory and the SCSI bus for transferring the data file from the dual-port memory to the hard disk over the SCSI bus and reciprocally.

公开(公告)号：FR2794259A1

公开(公告)日：2000-12-01

申请号：FR0006085

申请日：2000-05-12

Applicant: IBM

Inventor： BENAYOUN ALAIN ,  MICHEL PATRICK ,  LE PENNEC JEAN FRANCOIS ,  PIN CLAUDE

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/28

Abstract: Only one of activation blocks (22-30) associated with the corresponding selected decision block is activated to execute specific micro-instructions. A micro-instructions selection block (46) controls each activation blocks destine for selecting specific micro-instructions among a set of micro-instructions resulting from a content of an operand field of a given instruction.

公开(公告)号：FR2794259B1

公开(公告)日：2002-02-22

申请号：FR0006085

申请日：2000-05-12

Applicant: IBM

Inventor： BENAYOUN ALAIN ,  MICHEL PATRICK ,  LE PENNEC JEAN FRANCOIS ,  PIN CLAUDE

IPC: G06F9/38 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/28

Abstract: The present invention is directed to a hardware device for parallel processing a determined instruction of a set of programmable instructions having a same format with an operand field defining the execution steps of the instruction corresponding to the execution of micro-instructions, comprising decision blocks (12-20) being each associated with a specific instruction of the set of programmable instructions, only one decision block being selected by the determined instruction in order to define which are the specific micro-instructions to be processed for executing the determined instruction, activation blocks (22-30) respectively associated with the decision blocks for running one or several specific micro-instructions, only the activation block associated with said selected decision block being activated to run the specific micro-instructions, and a micro-instruction selection block (46) connected to each activation block for selecting the specific micro-instructions to be executed.

公开(公告)号：FR2803672A1

公开(公告)日：2001-07-13

申请号：FR0014658

申请日：2000-11-14

Applicant: IBM

Inventor： BENAYOUN ALAIN ,  MICHEL PATRICK ,  LE PENNEC JEAN FRANCOIS ,  PIN CLAUDE

IPC: G06F13/12 ,  G06F13/38

Abstract: The double access memory serves as a buffer between the web download and the local hard disc. The system provides transfer of files of data from a web server to a client work station via a network and vice versa. The client work station comprises a hard disc (205) for recording the file of data transferred via a SCSI bus (208). The client work station comprises a double access memory (304) for provisionally holding the file of data. A network logic unit (302) is interconnected between the network and the input port of the memory. A SCSI logic unit (303) is interconnected between the output port of the double access memory and the SCSI bus for transferring the data file from the double access memory to the hard disc, via the SCSI bus, and vice versa.

公开(公告)号：CA1313412C

公开(公告)日：1993-02-02

申请号：CA597345

申请日：1989-04-20

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  FERAUD JACQUES ,  NAUDIN BERNARD ,  PIN CLAUDE ,  SAINT-GEORGES ERIC

IPC: H04L29/02 ,  H04L29/06 ,  H04L29/08 ,  H04L12/00 ,  G06F15/80

Abstract: FR 9 88 005 PARALLEL PROCESSING METHOD AND DEVICE FOR RECEIVING AND TRANSMITTING HDLC SDLC BIT STREAMS This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6. (Figure 2)