公开(公告)号：AT544115T

公开(公告)日：2012-02-15

申请号：AT08775366

申请日：2008-07-29

Applicant: IBM

Inventor： CLARK LEO ,  FIELDS JAMES ,  GUTHRIE GUY ,  STARKE WILLIAM ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

IPC: G06F12/08

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.