公开(公告)号：GB2516083A

公开(公告)日：2015-01-14

申请号：GB201312417

申请日：2013-07-11

Applicant: IBM

Inventor： NORTH GERAINT ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  WILLIAMS PHILIP ,  SHEN HUGH ,  NAYAR NARESH

IPC: G06F12/08 ,  G06F9/455 ,  G06F11/14 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/109 ,  G06F12/12

Abstract: A system comprises a processor running a hypervisor for virtual machines (VMs), a cache, e.g. a write-back cache, and a memory storing VM images for a differential check-pointing failover technique. The cache comprises rows having a memory address, a cache line, and an image modification flag. The modification flag is set (430) when a cache line is modified (420) by a backed-up VM (425), for which an image is saved in memory, while hypervisor actions in privilege mode do not set the flag. Flagged cache lines addresses are written in a log of the memory upon eviction (440) or during periodic checkpoints. Replication of the VM image in another memory can be obtained by fetching the cache lines stored at the logged addresses. Using the modification bit flag instead of dirty bit tags ensures that modified cache lines are written to the log without being flushed at the same time.

公开(公告)号：GB2502663A

公开(公告)日：2013-12-04

申请号：GB201303302

申请日：2013-02-25

Applicant: IBM

Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

IPC: G06F12/12 ,  G06F12/08

Abstract: A deallocate request specifying a target address associated with a target cache line is sent from processor core to lower level cache; if the request hits, replacement order of lower level cache is updated such that the target is more likely to be evicted (e.g. making the target line least recently used [LRU]) in response to a subsequent cache miss. On a subsequent miss, the target line is cast out to the lower level cache with an indication that the line was deallocation request target (e.g. by setting a field in directory). The lower level cache may include load and store pipelines, with the deallocation request sent to the load pipeline. The deallocation may be executed at completion of dataset processing. Lower cache may include state machines servicing data requests, with retaining and updating performed without allocation of state machine/s to the request. A previous coherence state of the target may be retained. An interconnect fabric may connect processing units.

公开(公告)号：GB2502662A

公开(公告)日：2013-12-04

申请号：GB201303300

申请日：2013-02-25

Applicant: IBM

Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK EDWARD ,  WILLIAMS PHILIP

IPC: G06F12/12 ,  G06F12/08

Abstract: A deallocate request specifying a target address associated with a target cache line is sent from processor core to lower level cache; if the request hits the replacement order of the lower level cache is updated such that the target is more likely to be evicted (e.g. making the target line least recently used [LRU]) in response to a subsequent cache miss. The replacement order may not be updated with further accesses to target cache line prior to eviction. The lower cache may include load and store pipelines, with deallocation requests sent to the load pipeline. The deallocate instruction may be executed at completion dataset processing, and may be sent to lower level cache regardless of hitting in the upper cache. Lower cache may include state machines servicing data requests, with retaining and updating performed without allocation of state machine/s to the request. A compiler may insert the deallocation instruction into program code executed by the processor core, in response to the detection of an end of dataset processing. An interconnect fabric may couple the processing units.

公开(公告)号：GB2502663B

公开(公告)日：2014-07-30

申请号：GB201303302

申请日：2013-02-25

Applicant: IBM

Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

IPC: G06F12/12 ,  G06F12/08

Abstract: In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.

公开(公告)号：GB2502662B

公开(公告)日：2014-07-30

申请号：GB201303300

申请日：2013-02-25

Applicant: IBM

Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK EDWARD ,  WILLIAMS PHILIP

IPC: G06F12/12 ,  G06F12/08

公开(公告)号：AT544115T

公开(公告)日：2012-02-15

申请号：AT08775366

申请日：2008-07-29

Applicant: IBM

Inventor： CLARK LEO ,  FIELDS JAMES ,  GUTHRIE GUY ,  STARKE WILLIAM ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

IPC: G06F12/08

Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.