1.
    发明专利
    未知

    公开(公告)号:AT544115T

    公开(公告)日:2012-02-15

    申请号:AT08775366

    申请日:2008-07-29

    Applicant: IBM

    Abstract: A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

    3.
    发明专利
    未知

    公开(公告)号:AT502336T

    公开(公告)日:2011-04-15

    申请号:AT07857301

    申请日:2007-12-07

    Applicant: IBM

    Abstract: A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.

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