CIRCUITS AND METHODS FOR IMPLEMENTING POWER AMPLIFIERS FOR MILLIMETER WAVE APPLICATIONS
    4.
    发明申请
    CIRCUITS AND METHODS FOR IMPLEMENTING POWER AMPLIFIERS FOR MILLIMETER WAVE APPLICATIONS 审中-公开
    用于实施用于微波波形应用的功率放大器的电路和方法

    公开(公告)号:WO2006124087A2

    公开(公告)日:2006-11-23

    申请号:PCT/US2006005012

    申请日:2006-02-10

    Abstract: Circuits and methods are provided for implementing highly efficient switch-mode power amplifiers using BJTs (bipolar junction transistors) as active switching devices at millimeter- wave frequencies. For example, a power amplifier circuit (100) includes an active switch device comprising a BJT (bipolar junction transistor) (Tl) and an input network (105), (106) coupled to a base of the BJT (Tl) to drive the active switch device to achieve highly efficient switch-mode (e.g., Class E) operation at millimeter wave frequencies (e.g., 60 GHz). The input network (105), (106), which may be a passive or active driver network, is designed to provide optimal driving conditions. For instance, the input network (105), (106) is designed to present a real input impedance in a range of about 7 Ohms to about 15 Ohms as seen from the base of the active switch device (Tl). Another optimal driving condition includes the input network (105), (106) being designed to provide an asymmetrical drive current to the base of the active switch device (Tl), wherein the negative peak base current exceeds the positive peak base current. Further, the input network is designed to provide an asymmetrical drive base current to the active switch device (Tl) such that the base voltage has a swing that does not exceed about 400 mVpp (millivolts peak-to-peak).

    Abstract translation: 提供电路和方法,用于实现使用BJT(双极结型晶体管)作为毫米波频率的有源开关器件的高效开关模式功率放大器。 例如,功率放大器电路(100)包括有源开关器件,其包括耦合到BJT(T1)的基极的BJT(双极结型晶体管)(T1)和输入网络(105)(106),以驱动 主动开关装置,以实现毫米波频率(例如,60GHz)下的高效开关模式(例如,E类)操作。 可以是被动或主动的驱动器网络的输入网络(105)(106)被设计成提供最佳驾驶条件。 例如,输入网络(105)(106)被设计成在从有源开关器件(T1)的基极看到的情况下,呈现大约7欧姆到大约15欧姆的范围内的实际输入阻抗。 另一个最佳驱动条件包括输入网络(105),(106)被设计成向有源开关器件(T1)的基极提供非对称驱动电流,其中负峰值基极电流超过正峰值基极电流。 此外,输入网络被设计为向有源开关器件(T1)提供不对称驱动基极电流,使得基极电压具有不超过约400mVpp(毫伏峰峰值)的摆幅。

    RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S) IN RING AND/OR OFFSET CAVITIES

    公开(公告)号:CA2713353A1

    公开(公告)日:2009-10-22

    申请号:CA2713353

    申请日:2008-12-30

    Applicant: IBM

    Abstract: A radio-frequency integrated circuit chip package has N integrated aperture-coupled patch antennas, N being at least two, and includes N generally planar patches, and at least one generally planar ground plane. The ground plane is formed with at least N coupling aperture slots therein. N feed lines are spaced inwardly from the ground plane and substantially parallel thereto, and at least one radio-frequency chip is spaced inwardly from the feed lines and coupled to the feed lines and the ground plane. A first substrate layer is formed with the chip located in a chip-receiving cavity. A second substrate layer is interposed be-tween the ground plane and a plane defined by the patch. The patch is formed in a first metal layer, the ground plane in a second metal layer, and the second substrate layer defines an antenna cavity in which the N generally planar patches are located.

    RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S) IN RING AND/OR OFFSET CAVITIES

    公开(公告)号:CA2713353C

    公开(公告)日:2014-06-10

    申请号:CA2713353

    申请日:2008-12-30

    Applicant: IBM

    Abstract: A radio-frequency integrated circuit chip package has N integrated aperture-coupled patch antennas, N being at least two, and includes N generally planar patches, and at least one generally planar ground plane. The ground plane is formed with at least N coupling aperture slots therein. N feed lines are spaced inwardly from the ground plane and substantially parallel thereto, and at least one radio-frequency chip is spaced inwardly from the feed lines and coupled to the feed lines and the ground plane. A first substrate layer is formed with the chip located in a chip-receiving cavity. A second substrate layer is interposed be-tween the ground plane and a plane defined by the patch. The patch is formed in a first metal layer, the ground plane in a second metal layer, and the second substrate layer defines an antenna cavity in which the N generally planar patches are located.

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