Abstract:
PROBLEM TO BE SOLVED: To provide an on-chip circuit pad used on a lossy substrate to improve substrate induced losses. SOLUTION: A shielded circuit pad is provided where parasitic capacitance is controlled by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave application. The circuit pad is located on the substrate with a shield located beneath the circuit pad, and the shunt transmission line stub attached to the circuit pad. Accordingly, controlled impedance is obtained for the millimeter-wave application. The space between the circuit pad and the shield may then be minimized. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
Circuits and methods are provided for implementing highly efficient switch-mode power amplifiers using BJTs (bipolar junction transistors) as active switching devices at millimeter- wave frequencies. For example, a power amplifier circuit (100) includes an active switch device comprising a BJT (bipolar junction transistor) (Tl) and an input network (105), (106) coupled to a base of the BJT (Tl) to drive the active switch device to achieve highly efficient switch-mode (e.g., Class E) operation at millimeter wave frequencies (e.g., 60 GHz). The input network (105), (106), which may be a passive or active driver network, is designed to provide optimal driving conditions. For instance, the input network (105), (106) is designed to present a real input impedance in a range of about 7 Ohms to about 15 Ohms as seen from the base of the active switch device (Tl). Another optimal driving condition includes the input network (105), (106) being designed to provide an asymmetrical drive current to the base of the active switch device (Tl), wherein the negative peak base current exceeds the positive peak base current. Further, the input network is designed to provide an asymmetrical drive base current to the active switch device (Tl) such that the base voltage has a swing that does not exceed about 400 mVpp (millivolts peak-to-peak).
Abstract:
A radio-frequency integrated circuit chip package has N integrated aperture-coupled patch antennas, N being at least two, and includes N generally planar patches, and at least one generally planar ground plane. The ground plane is formed with at least N coupling aperture slots therein. N feed lines are spaced inwardly from the ground plane and substantially parallel thereto, and at least one radio-frequency chip is spaced inwardly from the feed lines and coupled to the feed lines and the ground plane. A first substrate layer is formed with the chip located in a chip-receiving cavity. A second substrate layer is interposed be-tween the ground plane and a plane defined by the patch. The patch is formed in a first metal layer, the ground plane in a second metal layer, and the second substrate layer defines an antenna cavity in which the N generally planar patches are located.
Abstract:
A radio-frequency integrated circuit chip package has N integrated aperture-coupled patch antennas, N being at least two, and includes N generally planar patches, and at least one generally planar ground plane. The ground plane is formed with at least N coupling aperture slots therein. N feed lines are spaced inwardly from the ground plane and substantially parallel thereto, and at least one radio-frequency chip is spaced inwardly from the feed lines and coupled to the feed lines and the ground plane. A first substrate layer is formed with the chip located in a chip-receiving cavity. A second substrate layer is interposed be-tween the ground plane and a plane defined by the patch. The patch is formed in a first metal layer, the ground plane in a second metal layer, and the second substrate layer defines an antenna cavity in which the N generally planar patches are located.