公开(公告)号：WO2007088127B1

公开(公告)日：2007-11-15

申请号：PCT/EP2007050652

申请日：2007-01-23

Applicant: IBM ,  IBM UK ,  REYNOLDS SCOTT KEVIN ,  BEUKEMA TROY JAMES

Inventor： REYNOLDS SCOTT KEVIN ,  BEUKEMA TROY JAMES

IPC: H03D5/00 ,  H03D1/00 ,  H04B1/00

CPC classification number: H04B1/005 ,  H03D1/229 ,  H03D3/007 ,  H03D5/00

Abstract: This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (> 30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. The architecture for supporting both quadrature down-conversion and ASK/AM is described first, followed by the ASK/AM detector circuit details, then the AM-FM detector architecture, and finally the most general AM-FM/IQ demodulator system concept and the FSK/FM detector circuit details.

公开(公告)号：WO2007088127A3

公开(公告)日：2007-09-27

申请号：PCT/EP2007050652

申请日：2007-01-23

Applicant: IBM ,  IBM UK ,  REYNOLDS SCOTT KEVIN ,  BEUKEMA TROY JAMES

Inventor： REYNOLDS SCOTT KEVIN ,  BEUKEMA TROY JAMES

IPC: H03D5/00 ,  H03D1/00 ,  H04B1/00

CPC classification number: H04B1/005 ,  H03D1/229 ,  H03D3/007 ,  H03D5/00

Abstract: This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (> 30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. The architecture for supporting both quadrature down-conversion and ASK/AM is described first, followed by the ASK/AM detector circuit details, then the AM-FM detector architecture, and finally the most general AM-FM/IQ demodulator system concept and the FSK/FM detector circuit details.

Abstract translation: 本公开涉及使用毫米波范围内的载波频率（> 30GHz）通过无线链路提供千兆位速率数据传输。 更具体地说，描述了可容易地结合到集成电路接收机系统中的用于检测幅移键控（ASK）或其他幅度调制（AM）的电路，使接收机能够支持复数IQ调制方案和更简单， 非相干开关或多级键控信号。 还描述了若干新颖的无线电架构，其通过添加鉴频器网络，具有处理频移键控（FSK）或其他频率调制（FM）以及AM和复杂IQ调制方案的能力。 这些无线电体系结构通过高效共享检测器硬件组件来支持各种各样的调制。 首先描述支持正交下变频和ASK / AM的架构，接下来是ASK / AM检测器电路细节，然后是AM-FM检测器架构，最后是最一般的AM-FM / IQ解调器系统概念和 FSK / FM检测器电路的详细信息。

公开(公告)号：EP1882305A4

公开(公告)日：2010-07-21

申请号：EP06734926

申请日：2006-02-10

Applicant: IBM

Inventor： FLOYD BRIAN A ,  GARCIA ALBERTO VALDES ,  PFEIFFER ULLRICH R ,  REYNOLDS SCOTT KEVIN

IPC: H03F3/217 ,  H03F3/04

CPC classification number: H03F3/2176 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/75

公开(公告)号：WO2006124087A2

公开(公告)日：2006-11-23

申请号：PCT/US2006005012

申请日：2006-02-10

Applicant: IBM ,  FLOYD BRIAN A ,  GARCIA ALBERTO VALDES ,  PFEIFFER ULLRICH R ,  REYNOLDS SCOTT KEVIN

Inventor： FLOYD BRIAN A ,  GARCIA ALBERTO VALDES ,  PFEIFFER ULLRICH R ,  REYNOLDS SCOTT KEVIN

IPC: H03F3/217

CPC classification number: H03F3/2176 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/75

Abstract: Circuits and methods are provided for implementing highly efficient switch-mode power amplifiers using BJTs (bipolar junction transistors) as active switching devices at millimeter- wave frequencies. For example, a power amplifier circuit (100) includes an active switch device comprising a BJT (bipolar junction transistor) (Tl) and an input network (105), (106) coupled to a base of the BJT (Tl) to drive the active switch device to achieve highly efficient switch-mode (e.g., Class E) operation at millimeter wave frequencies (e.g., 60 GHz). The input network (105), (106), which may be a passive or active driver network, is designed to provide optimal driving conditions. For instance, the input network (105), (106) is designed to present a real input impedance in a range of about 7 Ohms to about 15 Ohms as seen from the base of the active switch device (Tl). Another optimal driving condition includes the input network (105), (106) being designed to provide an asymmetrical drive current to the base of the active switch device (Tl), wherein the negative peak base current exceeds the positive peak base current. Further, the input network is designed to provide an asymmetrical drive base current to the active switch device (Tl) such that the base voltage has a swing that does not exceed about 400 mVpp (millivolts peak-to-peak).

Abstract translation: 提供电路和方法，用于实现使用BJT（双极结型晶体管）作为毫米波频率的有源开关器件的高效开关模式功率放大器。 例如，功率放大器电路（100）包括有源开关器件，其包括耦合到BJT（T1）的基极的BJT（双极结型晶体管）（T1）和输入网络（105）（106），以驱动 主动开关装置，以实现毫米波频率（例如，60GHz）下的高效开关模式（例如，E类）操作。 可以是被动或主动的驱动器网络的输入网络（105）（106）被设计成提供最佳驾驶条件。 例如，输入网络（105）（106）被设计成在从有源开关器件（T1）的基极看到的情况下，呈现大约7欧姆到大约15欧姆的范围内的实际输入阻抗。 另一个最佳驱动条件包括输入网络（105），（106）被设计成向有源开关器件（T1）的基极提供非对称驱动电流，其中负峰值基极电流超过正峰值基极电流。 此外，输入网络被设计为向有源开关器件（T1）提供不对称驱动基极电流，使得基极电压具有不超过约400mVpp（毫伏峰峰值）的摆幅。

公开(公告)号：DE112012003358T5

公开(公告)日：2014-04-30

申请号：DE112012003358

申请日：2012-06-21

Applicant: IBM

Inventor： REYNOLDS SCOTT KEVIN ,  LIU DUIXIAN ,  NATARAJAN ARUN SRIDHAR ,  FRIEDMAN DANIEL JOSEPH ,  VALDEZ GARCIA ALBERTO

IPC: H01Q1/00 ,  H01L23/538

Abstract: Systeme, Verfahren, Einheiten und Vorrichtungen, die auf Transceiver-Einheiten gerichtet sind, werden offenbart. Gemäß einem Verfahren wird eine erste Gruppe von Antennenpositionen in einem ersten Abschnitt aus einer Gruppe von Abschnitten eines Schaltungslayouts für die Schaltkreisbaugruppe ausgewählt. Das Verfahren enthält ferner Auswählen einer weiteren Gruppe von Antennenpositionen in einem weiteren Abschnitt des Schaltungslayouts, so dass eine Anordnung von ausgewählten Antennenpositionen der weiteren Gruppe von einer Anordnung von ausgewählten Antennenpositionen einer zuvor ausgewählten Gruppe von Antennenpositionen verschieden ist. Das Auswählen einer weiteren Gruppe von Positionen in einem weiteren Abschnitt wird wiederholt, bis für eine Gesamtzahl von Antennen Auswahlen getroffen wurden. Das Auswählen der weiteren Gruppe wird so ausgeführt, dass aufeinanderfolgende nicht ausgewählte Positionen in dem weiteren Abschnitt eine im Voraus festgelegte Anzahl von Positionen nicht übersteigen. Außerdem werden Antennenelemente an den ausgewählten Positionen gebildet, um die Schaltkreisbaugruppe herzustellen.

公开(公告)号：DE69637333T2

公开(公告)日：2008-10-02

申请号：DE69637333

申请日：1996-06-12

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  DELIGIANNI HARIKLIA ,  HARPER JAMES MCKELL EDWIN ,  HU CHAO-KUN ,  PEARSON DALE JONATHAN ,  REYNOLDS SCOTT KEVIN ,  TU KING-NING ,  UZOH CYPRIAN EMEKA

IPC: C22C9/00 ,  H01L23/532 ,  C22C9/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

公开(公告)号：DE69637333D1

公开(公告)日：2008-01-10

申请号：DE69637333

申请日：1996-06-12

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  DELIGIANNI HARIKLIA ,  HARPER JAMES MCKELL EDWIN ,  HU CHAO-KUN ,  PEARSON DALE JONATHAN ,  REYNOLDS SCOTT KEVIN ,  TU KING-NING ,  UZOH CYPRIAN EMEKA

IPC: C22C9/00 ,  H01L23/532 ,  C22C9/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

Abstract: Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

公开(公告)号：IE960781A1

公开(公告)日：1997-07-02

申请号：IE960781

申请日：1996-11-06

Applicant: IBM

Inventor： PEARSON DALE JONATHAN ,  REYNOLDS SCOTT KEVIN

IPC: H03K19/013 ,  H03K19/017 ,  H03K19/086 ,  H03K19/094 ,  H03K19/173 ,  H03K19/01

Abstract: This invention provides a circuit means and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a means and method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings. The output is sampled and maintained at near ideal bias voltage with a voltage follower type circuit which provides a gain of less than unit and finite delay. Particular circuit implementations using various semiconductor technologies are described and many others are possible. Although the invention may find primary use in VLSI logic circuits, especially those requiring high speed and low power, it is also shown to be useful in analog circuits. Alternate circuit configurations for dynamically biased active load devices are described.

公开(公告)号：GB2494497B

公开(公告)日：2013-11-27

申请号：GB201210868

申请日：2012-06-20

Applicant: IBM

Inventor： SADHU BODHISATWA ,  PLOUCHART JEAN-OLIVIER ,  TIERNO JOSE ,  RYLYAKOV ALEXANDER ,  REYNOLDS SCOTT KEVIN

IPC: H03B5/12

Abstract: There is provided a tank based oscillator. The oscillator includes one or more active devices, one or more passive devices, and a tank circuit decoupled from the active devices using at least one of the one or more passive devices. A coupling ratio between the tank circuit and the one or more active devices is set such that a maximum value of an oscillation amplitude of the tank circuit is limited based upon a breakdown of only the one or more passive devices.

公开(公告)号：GB2494497A

公开(公告)日：2013-03-13

申请号：GB201210868

申请日：2012-06-20

Applicant: IBM

Inventor： SADHU BODHISATWA ,  PLOUCHART JEAN-OLIVIER ,  TIERNO JOSE ,  RYLYAKOV ALEXANDER ,  REYNOLDS SCOTT KEVIN

IPC: H03B5/12

Abstract: An oscillator includes an LC tank circuit 140, active devices 131 & 132 and capacitors (passive devices) Ct and Cd. The tank circuit 140 is indirectly coupled to the active devices 131, 132 via the capacitors. The amplitude of the oscillation in the tank circuit 140 is reduced by a divider formed by capacitors Cd and Ct (see fig.2) before application to the gates of the active devices 131 & 132. The division ratio ( coupling ratio ) between the tank circuit 140 and the active devices 131, 132 allows an amplitude of oscillation in the tank circuit that would otherwise cause breakdown of the active devices. The maximum amplitude is now limited by the breakdown of the passive devices. In an embodiment, the oscillation amplitude may be 40V and the capacitive divider reduces and decouples this from the active devices which may have breakdown voltages of around 1V. The use of a high amplitude oscillation in the tank circuit gives low phase noise. It is also disclosed that the oscillation amplitude is highest and phase noise lowest if the biasing inductors 111 & 112 are tuned just below the oscillation frequency of the tank circuit 140.