中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.031 seconds)

    PROCESS FOR FORMING A NARROW MESA ON A SUBSTRATE AND PROCESS FOR MAKING A SELF-ALIGNED GATE FIELD EFFECT TRANSISTOR
    1.
    发明专利
    PROCESS FOR FORMING A NARROW MESA ON A SUBSTRATE AND PROCESS FOR MAKING A SELF-ALIGNED GATE FIELD EFFECT TRANSISTOR 未知

    公开(公告)号：DE3467832D1

    公开(公告)日：1988-01-07

    申请号：DE3467832

    申请日：1984-05-16

    Applicant: IBM

    Inventor： FOWLER ALAN BICKSLER ,  HARTSTEIN ALLAN MARK

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L21/28 ,  H01L29/08

    Abstract: A mesa is formed on a substrate by providing a vertical step in a layer (5; 25) of non-metallic material (eg silicon dioxide) formed on the substrate; vapour depositing a layer (7; 27) of metal (eg aluminium or gold) over the layer of nonmetallic material at an angle sufficient to provide a thicker metal deposit adjacent to the step than over the horizontal surface of the non-metallic material; removing the thinner portion of the metal layer to provide a very narrow metal mask (7, 27,) adjacent the step in the layer (5; 25) of non-metallic material; and etching away all of the layer (5; 25) of non-metallic material not covered by the very narrow metal mask down to the substrate. A self-aligned gate field effect transistor can be made by forming a mesa of isolation material on a semiconductor substrate by a process as described in the preceding paragraph and depositing doped semiconductor material (8, 9, 10; 28, 29, 30) on the horizontal surfaces of the substrate at both sides of the mesa and on the top of the mesa. The doped material (10, 30) on top of the mesa can be used as a gate or alternatively the mesa and the doped material on top of it can be removed, and the exposed substrate surface then oxidised to provide a gate oxide (31) and a gate (33) formed over the gate oxide.

    6.
    发明专利
    未知

    公开(公告)号：DE3584799D1

    公开(公告)日：1992-01-16

    申请号：DE3584799

    申请日：1985-06-19

    Applicant: IBM

    Inventor： FOWLER ALAN BICKSLER

    IPC: H01L29/812 ,  H01L21/338 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/80 ,  H01L29/76 ,  H01L29/10 ,  G01B9/02

    Abstract: An electron interferometer device includes a heterojunction comprised by first (1, 2) and second (5, 6) semiconductor materials, the first material having a greater band gap than the second material. The first semiconductor material provides a pair of conductive paths (9, 10) closely adjacent to the interface (3) of the heterojunction and connected in parrel. A gate electrode (12) is used to impress a localised electric field through one (9) of the conductive paths in a direction perpendicular to the heterjunction in order to change the electron wavelength in that conductive path.

    TRANSISTOR WITH TUNNEL EMITTER AND UPPER ENERGY VALLEY BASE
    8.
    发明专利
    TRANSISTOR WITH TUNNEL EMITTER AND UPPER ENERGY VALLEY BASE 未知

    公开(公告)号：DE3262514D1

    公开(公告)日：1985-04-18

    申请号：DE3262514

    申请日：1982-03-18

    Applicant: IBM

    Inventor： DUMKE WILLIAM PAUL ,  FOWLER ALAN BICKSLER

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/267 ,  H01L29/68 ,  H01L29/76 ,  H01L29/72 ,  H01L29/08

    Abstract: In a transistor capable of operation at very high speed, the emitter comprises an outer region (8) having a normal energy level for charge carriers of the higher mobility type (electrons) and an inner region (9) providing a barrier having a height greater than the aforesaid normal energy level and being sufficiently thin to permit the higher mobility charge carriers to quantum mechanical tunnel therethrough. The base (3) has an upper energy valley for the injected charge carriers substantially at the aforementioned normal energy level in the outer region of the emitter and is sufficiently thin to permit rapid transport therethrough of the injected charge carriers. The collector comprises an inner region (12) providing a barrier having a height at least as high as the upper energy valley in the base and an outer region (13) having a normal energy level for the injected charge carriers lower than the normal energy level for those charge carriers in the outer region (8) of the emitter. Because the injected charge carriers cross the base in an upper energy valley, the probability of energy loss is reduced. The switching time of the transistor is of the order of 10 seconds.

    9.
    发明专利
    未知

    公开(公告)号：DE1282210B

    公开(公告)日：1968-11-07

    申请号：DEJ0027467

    申请日：1965-02-06

    Applicant: IBM

    Inventor： FOWLER ALAN BICKSLER

    IPC: G02F3/00 ,  H01S5/062 ,  H01S5/10 ,  H01S5/50 ,  H01S3/18

    Abstract: 1,079,813. Lasers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 15, 1965 [Feb. 10, 1964], No. 1799/65. Heading H1C. Two PN junction injection lasers 10, 11 having a common longitudinal axis and their PN junctions coplanar are spaced apart along their common axis, the combined threshold currents being less than the sum of the individual threshold currents of the lasers. The two lasers 10, 11 are fabricated from the same crystalline body and mounted on a support 12 about 15 microns apart. When the lasers are energized by current from sources 13, 14 light from laser 10 passes into laser 11 and is amplified thereby to produce a light output as shown. There will only be an output when current is applied to both lasers and the arrangement functions as an AND circuit. It is stated that the threshold current for the coupled lasers is less than that for the individual lasers. One of the lasers may be longer than the other.

Patent Agency Ranking