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    1.
    发明专利
    未知

    公开(公告)号：DE3675236D1

    公开(公告)日：1990-12-06

    申请号：DE3675236

    申请日：1986-03-04

    Applicant: IBM

    Inventor： BEHA JOHANNES GEORG ,  DREYFUS RUSSELL EARREN ,  HARTSTEIN ALLAN MARK ,  RUBLOFF GARY WAYNE

    IPC: G01R31/28 ,  G01R31/308 ,  H01L21/66 ,  H01L23/544

    Abstract: The method comprising covering metal test pads (4) of an integrated circuit chip-to-test (11), with a photon-transmissive passivation layer (2) susceptible to photon assisted tunneling, covering the layer (2) with a thin conductive photon-transparent overlayer (3), and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, thus providing a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads.

    2.
    发明专利
    未知

    公开(公告)号：DE68927826D1

    公开(公告)日：1997-04-10

    申请号：DE68927826

    申请日：1989-12-30

    Applicant: IBM

    Inventor： HARTSTEIN ALLAN MARK ,  KOCH ROGER HILSEN

    IPC: G06G7/60 ,  G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  H01L29/78 ,  H03K19/00 ,  G11C15/04 ,  G06F15/80

    Abstract: A neural network utilizing the threshold characteristics of a semiconductor device as the various memory elements of the network. Each memory element comprises a complementary pair of MOSFETs in which the threshold voltage is adjusted as a function of the input voltage to the element. The network is able to learn by example using a local learning algorithm. The network includes a series of output amplifiers in which the output is provided by the sum of the outputs of a series of learning elements coupled to the amplifier. The output of each learning element is the difference between the input signal to each learning element and an individual learning threshold at each input. The learning is accomplished by charge trapping in the insulator of each individual input MOSFET pair. The thresholds of each transistor automatically adjust to both the input and output voltages to learn the desired state. After input patterns have been learned by the network, the learning function is set to zero so that the thresholds remain constant and the network will come to an equilibrium state under the influence of a test input pattern thereby providing, as an output, the learned pattern most closely resembling the test input pattern.

    PROCESS FOR FORMING A NARROW MESA ON A SUBSTRATE AND PROCESS FOR MAKING A SELF-ALIGNED GATE FIELD EFFECT TRANSISTOR
    5.
    发明专利
    PROCESS FOR FORMING A NARROW MESA ON A SUBSTRATE AND PROCESS FOR MAKING A SELF-ALIGNED GATE FIELD EFFECT TRANSISTOR 未知

    公开(公告)号：DE3467832D1

    公开(公告)日：1988-01-07

    申请号：DE3467832

    申请日：1984-05-16

    Applicant: IBM

    Inventor： FOWLER ALAN BICKSLER ,  HARTSTEIN ALLAN MARK

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L21/28 ,  H01L29/08

    Abstract: A mesa is formed on a substrate by providing a vertical step in a layer (5; 25) of non-metallic material (eg silicon dioxide) formed on the substrate; vapour depositing a layer (7; 27) of metal (eg aluminium or gold) over the layer of nonmetallic material at an angle sufficient to provide a thicker metal deposit adjacent to the step than over the horizontal surface of the non-metallic material; removing the thinner portion of the metal layer to provide a very narrow metal mask (7, 27,) adjacent the step in the layer (5; 25) of non-metallic material; and etching away all of the layer (5; 25) of non-metallic material not covered by the very narrow metal mask down to the substrate. A self-aligned gate field effect transistor can be made by forming a mesa of isolation material on a semiconductor substrate by a process as described in the preceding paragraph and depositing doped semiconductor material (8, 9, 10; 28, 29, 30) on the horizontal surfaces of the substrate at both sides of the mesa and on the top of the mesa. The doped material (10, 30) on top of the mesa can be used as a gate or alternatively the mesa and the doped material on top of it can be removed, and the exposed substrate surface then oxidised to provide a gate oxide (31) and a gate (33) formed over the gate oxide.

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