公开(公告)号：WO2013102532A3

公开(公告)日：2013-08-29

申请号：PCT/EP2012074935

申请日：2012-12-10

Applicant: IBM ,  IBM UK

Inventor： FRAZIER GILES ROGER ,  NAYAR NARESH ,  MEALEY BRUCE

IPC: G06F9/455 ,  G06F9/38

CPC classification number: G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread- specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract translation: 用于在多个逻辑分区（LPAR）中模拟独占使用处理器核心的技术包括响应于LPAR的访问请求而提供硬件线程相关状态信息，所述访问请求反映了LPAR访问硬件线程相关的专用处理器 信息。 如果请求者是在低于管理程序特权级别的特权级别上执行的程序，则响应于访问请求而返回的信息被变换，使得每个逻辑分区都像处理器独占使用那样查看处理器。 该技术可以由处理器内核中的逻辑电路块来实现，该逻辑电路块将硬件线程特定信息变换成硬件线程特定信息的逻辑表示，或者该变换可以由中断处理程序的程序指令执行， 包含信息的物理寄存器。

公开(公告)号：JP2008171428A

公开(公告)日：2008-07-24

申请号：JP2008001409

申请日：2008-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FRAZIER GILES ROGER ,  CORRIGAN MICHAEL J ,  RICHARD LEWIS ARNT ,  ARMSTRONG WILLIAM JOSEPH ,  O'QUIN II JOHN THOMAS ,  NAYAR NARESH ,  MARCHINI TIMOTHY RICHARD ,  CATHY MAY

IPC: G06F9/30

CPC classification number: G06F9/30101 ,  G06F9/30181 ,  G06F9/468

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for selecting an architecture level to which a processor appears to conform in specification within a computing environment in order to achieve efficient program execution and migration among processor architectures with different levels.
SOLUTION: The method utilizes a processor compatibility register (PCR) that controls an architecture level that the processor appears to support. In one embodiment, the PCR is accessible only by super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program is designed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在计算环境中选择处理器看起来符合规范的体系结构级别的方法和系统，以便在具有不同级别的处理器架构之间实现有效的程序执行和迁移。 解决方案：该方法利用处理器兼容性寄存器（PCR）来控制处理器似乎支持的架构级别。 在一个实施方案中，PCR仅可由超级特权软件访问。 超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002305535A

公开(公告)日：2002-10-18

申请号：JP2001386626

申请日：2001-12-19

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  PFISTER GREGORY FRANCIS ,  RECIO RENATO JOHN

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/17 ,  H04L12/28 ,  H04L12/56 ,  H04L13/08 ,  H04L29/08

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and computer implemented instructions for transferring data. SOLUTION: A request is sent by a requester to a responder. The request includes the amount of available processing space at the requester. When the request is received from the responder, data are identified using the request. The data are placed into a plurality of subsequences of data packets for transfer to the requester, wherein each packet within the set of subsequences hold data in the amount less than or equal to the amount of available space. These subsequences are then sent to the requester one subsequence at a time. A new subsequence is sent each time the available processing space at the requester becomes free to process data from another subsequence.

公开(公告)号：GB2513266A

公开(公告)日：2014-10-22

申请号：GB201412799

申请日：2012-12-10

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  NAYAR NARESH ,  MEALEY BRUCE

IPC: G06F9/455

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread- specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

公开(公告)号：DE112016001686T5

公开(公告)日：2017-12-28

申请号：DE112016001686

申请日：2016-06-21

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  GSCHWIND MICHAEL KARL

IPC: G06F12/02

Abstract: Ermöglicht wird eine automatische Speicherbereinigungsverarbeitung. Auf Grundlage einer Ausführung eines Ladebefehls und einer Feststellung, dass sich eine Adresse eines zu ladenden Objektzeigers in einem Zeigerspeicherbereich befindet und dass der Objektzeiger eine Position innerhalb eines ausgewählten Arbeitsspeicherbereichs angibt, für den eine automatische Speicherbereinigung stattfindet, wird durch eine Routine, die innerhalb eines Prozessors der Datenverarbeitungsumgebung ausgeführt wird, eine Verarbeitungssteuerung erhalten. Die Routine erhält den Objektzeiger aus dem Zeigerspeicherbereich und ermittelt, ob der Objektzeiger modifiziert werden soll. Wenn der Objektzeiger modifiziert werden soll, modifiziert die Routine den Objektzeiger. Danach kann die Routine den modifizierten Objektzeiger in einer ausgewählten Position speichern.

公开(公告)号：GB2499487A

公开(公告)日：2013-08-21

申请号：GB201221914

申请日：2012-12-05

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  INDUKURU VENKAT RAJEEV ,  SPANNAUS JOHN FRED ,  MERICAS ALEXANDER ERIK

IPC: G06F11/34

Abstract: Disclosed is an event counter for electronic devices and a method of operation. The counter works by receiving a signal that indicates that an event in the device has occurred. The counter in then incremented each time a variable number of the events have occurred, and automatically increasing the variable number as the total count of events increases. The event counter may have a count mantissa and the variable number increases geometrically each time the count mantissa overflows. The count exponent may be incremented each time the count mantissa overflows, and the variable number is a pre-scale value equal to a counter base raised to the power of the value of the count exponent. The count mantissa may be set to a transitional value each time the count mantissa overflows, the transitional value equal to the overflow value of the count mantissa divided by the counter base.

公开(公告)号：DE2966055D1

公开(公告)日：1983-09-15

申请号：DE2966055

申请日：1979-12-04

Applicant: IBM

Inventor： FRAZIER GILES ROGER

IPC: H03M5/04 ,  G11B20/14 ,  H03M5/12 ,  H04L25/49 ,  G11B5/09 ,  G06F11/00 ,  H03K13/00

Abstract: A decoding technique applicable to binary data encoded by phase encoding (PE), frequency modulation (FM), or modified frequency modulation (MFM). Resynchronization of the decoding clocking circuitry occurs upon every flux transition, rather than at less than all flux transitions, such as only at each data flux transition in the case of phase encoding. The technique provides substantially greater velocity tolerance than previous techniques for decoding codes encoded in this manner.

公开(公告)号：DE112012005085T5

公开(公告)日：2014-08-28

申请号：DE112012005085

申请日：2012-12-10

Applicant: IBM

Inventor： NAYAR NARESH ,  MEALEY BRUCE ,  FRAZIER GILES ROGER

IPC: G06F9/455 ,  G06F9/38

Abstract: Techniken zum Simulieren einer ausschließlichen Nutzung eines Prozessorkerns unter mehreren logischen Partitionen (logical partitions (LPARs)) beinhalten als Reaktion auf Zugriffsanfragen durch die LPARs ein Bereitstellen hardware-strang-abhängiger Statusinformationen, die eine ausschließliche Nutzung des Prozessors durch die auf die hardware-strang-abhängigen Informationen zugreifende LPAR wiedergeben. Die als Reaktion auf die Zugriffsanfragen ausgegebenen Informationen werden umgewandelt, wenn es sich beim Anfrager um ein Programm handelt, das mit einer niedrigeren Berechtigungsebene als der Berechtigungsebene des Hypervisors ausgeführt wird, so dass jede logische Partition den Prozessor so wahrnimmt, als ob sie eine ausschließliche Nutzung des Prozessors besitzt. Die Techniken können durch einen logischen Schaltungsblock innerhalb des Prozessorkerns realisiert werden, welcher die hardware-strang-spezifischen Informationen in eine logische Darstellung der hardware-strang-spezifischen Informationen umwandelt, oder die Umwandlung kann durch Programmanweisungen eines Interrupt-Abwicklers durchgeführt werden, der einen Zugriff auf das die Informationen enthaltende physische Register unterbricht.

公开(公告)号：GB2499487B

公开(公告)日：2014-02-12

申请号：GB201221914

申请日：2012-12-05

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  INDUKURU VENKAT RAJEEV ,  SPANNAUS JOHN FRED ,  MERICAS ALEXANDER ERIK

IPC: G06F11/34

Abstract: Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.