公开(公告)号：WO2013102532A3

公开(公告)日：2013-08-29

申请号：PCT/EP2012074935

申请日：2012-12-10

Applicant: IBM ,  IBM UK

Inventor： FRAZIER GILES ROGER ,  NAYAR NARESH ,  MEALEY BRUCE

IPC: G06F9/455 ,  G06F9/38

CPC classification number: G06F21/6218 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/45541 ,  G06F9/45558 ,  G06F2009/45587

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread- specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract translation: 用于在多个逻辑分区（LPAR）中模拟独占使用处理器核心的技术包括响应于LPAR的访问请求而提供硬件线程相关状态信息，所述访问请求反映了LPAR访问硬件线程相关的专用处理器 信息。 如果请求者是在低于管理程序特权级别的特权级别上执行的程序，则响应于访问请求而返回的信息被变换，使得每个逻辑分区都像处理器独占使用那样查看处理器。 该技术可以由处理器内核中的逻辑电路块来实现，该逻辑电路块将硬件线程特定信息变换成硬件线程特定信息的逻辑表示，或者该变换可以由中断处理程序的程序指令执行， 包含信息的物理寄存器。

公开(公告)号：WO2007071606A3

公开(公告)日：2007-08-09

申请号：PCT/EP2006069672

申请日：2006-12-13

Applicant: IBM ,  IBM UK ,  ARIMILLI RAVI ,  GOVINDARAJU RAMA ,  HOCHSCHILD PETER ,  MEALEY BRUCE ,  SHARMA SATYA ,  SINHAROY BALARAM

Inventor： ARIMILLI RAVI ,  GOVINDARAJU RAMA ,  HOCHSCHILD PETER ,  MEALEY BRUCE ,  SHARMA SATYA ,  SINHAROY BALARAM

IPC: G06F9/315 ,  G06F12/08

CPC classification number: G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0897 ,  G06F2212/6028

Abstract: A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.

Abstract translation: 公开了用于基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。 该方法包括确定半同步存储器复制操作的开始。 在至少一个高速缓存注入位中检查半同步存储器复制操作的给定值。 响应于高速缓存注入位中的给定值，将预定义数量的目标数据行复制到至少一个高速缓存存储器中。

公开(公告)号：JP2002328891A

公开(公告)日：2002-11-15

申请号：JP2002046075

申请日：2002-02-22

Applicant: IBM

Inventor： ARNDT RICHARD L ,  FOSTER ROBERT K ,  LIPP WALTER M ,  LUCAS KERRY A ,  MCCREARY CASEY L ,  MEALEY BRUCE ,  POIMBOEUF JOSHUA N

IPC: G06F3/048 ,  G06F9/46 ,  G06F13/00 ,  G06F15/00 ,  G09G5/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for providing a computer system having a plurality of logical partitions with a virtual terminal. SOLUTION: The computer system is coupled to an external display device through a single communication interface. The method and system include allowing the logical partitions to share the communication interface by multiplexing communication to the display device for each of the logical partitions over the communication interface. Windows are displayed on the display device for each of the logical partitions, and the communication from each of the logical partitions is then routed to the corresponding window for display on the display device.

公开(公告)号：AU2011229395B2

公开(公告)日：2014-04-03

申请号：AU2011229395

申请日：2011-02-15

Applicant: IBM

Inventor： MOODY JAMES BERNARD ,  MEALEY BRUCE

IPC: G06F9/46

Abstract: A method, system, and computer usable program product for a dual mode reader writer lock. A contention condition is determined in using an original lock. The original lock manages read and write access to a resource by several processes executing in the data processing system. The embodiment creates a set of expanded locks for use in conjunction with the original lock. The original lock and the set of expanded locks forming the dual mode reader writer lock, which operates to manage the read and write access to the resource. Using an index within the original lock, each expanded lock is indexed such that each expanded lock is locatable using the index. The contention condition is resolved by distributing requests for acquiring and releasing the read access and write access to the resource by the several processes across the original lock and the set of expanded locks.

公开(公告)号：DE112012005085T5

公开(公告)日：2014-08-28

申请号：DE112012005085

申请日：2012-12-10

Applicant: IBM

Inventor： NAYAR NARESH ,  MEALEY BRUCE ,  FRAZIER GILES ROGER

IPC: G06F9/455 ,  G06F9/38

Abstract: Techniken zum Simulieren einer ausschließlichen Nutzung eines Prozessorkerns unter mehreren logischen Partitionen (logical partitions (LPARs)) beinhalten als Reaktion auf Zugriffsanfragen durch die LPARs ein Bereitstellen hardware-strang-abhängiger Statusinformationen, die eine ausschließliche Nutzung des Prozessors durch die auf die hardware-strang-abhängigen Informationen zugreifende LPAR wiedergeben. Die als Reaktion auf die Zugriffsanfragen ausgegebenen Informationen werden umgewandelt, wenn es sich beim Anfrager um ein Programm handelt, das mit einer niedrigeren Berechtigungsebene als der Berechtigungsebene des Hypervisors ausgeführt wird, so dass jede logische Partition den Prozessor so wahrnimmt, als ob sie eine ausschließliche Nutzung des Prozessors besitzt. Die Techniken können durch einen logischen Schaltungsblock innerhalb des Prozessorkerns realisiert werden, welcher die hardware-strang-spezifischen Informationen in eine logische Darstellung der hardware-strang-spezifischen Informationen umwandelt, oder die Umwandlung kann durch Programmanweisungen eines Interrupt-Abwicklers durchgeführt werden, der einen Zugriff auf das die Informationen enthaltende physische Register unterbricht.

公开(公告)号：CA2783449A1

公开(公告)日：2011-09-22

申请号：CA2783449

申请日：2011-02-15

Applicant: IBM

Inventor： MOODY JAMES BERNARD ,  MEALEY BRUCE

IPC: G06F9/46

Abstract: A method, system, and computer usable program product for a dual mode reader writer lock. A contention condition is determined in using an original lock. The original lock manages read and write access to a resource by several processes executing in the data processing system. The embodiment creates a set of expanded locks for use in conjunction with the original lock. The original lock and the set of expanded locks forming the dual mode reader writer lock, which operates to manage the read and write access to the resource. Using an index within the original lock, each expanded lock is indexed such that each expanded lock is locatable using the index. The contention condition is resolved by distributing requests for acquiring and releasing the read access and write access to the resource by the several processes across the original lock and the set of expanded locks.

公开(公告)号：CA2568747A1

公开(公告)日：2005-12-15

申请号：CA2568747

申请日：2005-05-18

Applicant: IBM

Inventor： MEALEY BRUCE ,  ASLOT VISHAL CHITTRANJAN

IPC: G06F9/46 ,  G06F12/00 ,  G06F12/10

Abstract: A system and method for extending the use of the cross-memory descriptor in a server partition environment such that it may be used to describe another partition's memory, e.g., a client partition's memory (referred to hereafter as a "remote" memory), are provided. With the system and method, when an operating system in a logically partitioned computing system is initialized, operating system kernel services are invoked that examine a device tree of the computing system and generate an extended cross-memory descriptor that describes the local memory of another logical partition, which is a remote memory to the present logical partition. When an access to a remote memory is required to perform an operation, the operating system of the server partition uses the stored extended cross-memory descriptor to perform the remote memory access.

公开(公告)号：DE112012005014B4

公开(公告)日：2022-02-03

申请号：DE112012005014

申请日：2012-11-21

Applicant: IBM

Inventor： STUECHELI JEFFREY A ,  RETTER ERIC EUGENE ,  RAJAMANI KARTHICK ,  MEALEY BRUCE ,  CARTER JOHN BRUCE

IPC: G06F7/38 ,  G06F7/58 ,  G06F7/76

Abstract: Verfahren in einem Datenverarbeitungssystem zum Ausführen einer arithmetischen Gleitkommaoperation, wobei das Verfahren aufweist:in der Hardwarelogik des Datenverarbeitungssystems Empfangen einer Vielzahl von Gleitkommaoperanden der arithmetischen Gleitkommaoperation;durch die Hardwarelogik Verschieben von Bits in einer Mantisse von mindestens einem Gleitkommaoperanden aus der Vielzahl von Gleitkommaoperanden;durch die Hardwarelogik Speichern von einem oder mehreren Bits der Mantisse, die aus einem Bitbereich der Mantisse des mindestens einen Gleitkommaoperanden heraus verschoben werden;durch die Hardwarelogik Erzeugen eines Vektorwerts, der auf dem bzw. den gespeicherten einen oder mehreren Bits der Mantisse beruht, die aus dem Bitbereich der signifikanten Bits des mindestens einen Gleitkommaoperanden heraus verschoben werden; unddurch die Hardwarelogik Erzeugen eines Ergebniswerts für die arithmetische Gleitkommaoperation auf der Grundlage des Vektorwerts und der Vielzahl der Gleitkommaoperandenwobei das Speichern von einem oder mehreren Bits der Mantisse, die aus einem Bitbereich der Mantisse des mindestens einen Gleitkommaoperanden heraus verschoben werden, aufweist: Setzen von Bits an Bitpositionen eines Sonderregisters, die dem einen oder den mehreren Bits der Mantisse entsprechen, die aus dem Bitbereich der Mantisse heraus verschoben werdenwobei zu jeder Bitposition in dem Sonderregister ein anderes Wahrscheinlichkeitsgewicht gehört und wobei das Erzeugen des Vektorwerts auf der Grundlage des Speicherns von einem oder mehreren Bits der Mantisse, die aus dem Bitbereich der Mantisse des mindestens einen Gleitkommaoperanden heraus verschoben werden, aufweist: Erzeugen des Vektorwerts auf der Grundlage von Wahrscheinlichkeitsgewichten, die zu den Bitpositionen gehören, für die entsprechende Bitwerte in dem Sonderregister gesetzt sind.

公开(公告)号：AU2011229395A1

公开(公告)日：2012-07-05

申请号：AU2011229395

申请日：2011-02-15

Applicant: IBM

Inventor： MOODY JAMES BERNARD ,  MEALEY BRUCE

IPC: G06F9/46

Abstract: A method, system, and computer usable program product for a dual mode reader writer lock. A contention condition is determined in using an original lock. The original lock manages read and write access to a resource by several processes executing in the data processing system. The embodiment creates a set of expanded locks for use in conjunction with the original lock. The original lock and the set of expanded locks forming the dual mode reader writer lock, which operates to manage the read and write access to the resource. Using an index within the original lock, each expanded lock is indexed such that each expanded lock is locatable using the index. The contention condition is resolved by distributing requests for acquiring and releasing the read access and write access to the resource by the several processes across the original lock and the set of expanded locks.

公开(公告)号：GB2513266A

公开(公告)日：2014-10-22

申请号：GB201412799

申请日：2012-12-10

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  NAYAR NARESH ,  MEALEY BRUCE

IPC: G06F9/455

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread- specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.