公开(公告)号：DE3279782D1

公开(公告)日：1989-07-27

申请号：DE3279782

申请日：1982-03-24

Applicant: IBM ,  IBM FRANCE

Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

IPC: G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  G11C8/00

Abstract: A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value ( phi ), the second one providing the complement ( phi ) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of ( phi ) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output phi . Transistor T11-2 in the second circuit prevents phi from going high as long as it is maintained on by the level provided by R10-1, R11-2 from phi .

公开(公告)号：DE69122491D1

公开(公告)日：1996-11-07

申请号：DE69122491

申请日：1991-02-28

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILLIPE ,  GRANDGUILLOT MICHEL

IPC: H03K3/356 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0944

Abstract: Input ECL level signals are received and converted into output CMOS level signals by an improved high-speed, low power consumption input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series as standard. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of a level-shifter circuit (20), which supplies two pairs of output signals (V1, V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The level-shifter circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4) and one NFET (N1; N2) serially connected. The common node (E; F) between the PFETs in one branch, is cross-coupled to the gate electrode of the NFET (N2; N1) of the other branch. The gate electrode of the PFET (P1; P2) connected to the emitter of the bipolar transistor (T1; T2) in one branch is driven by the potential of the common node formed by the other PFET (P4; P3) and the NFET (N2; N1) in the other branch. The IN PHASE (VOUT) and OUT OF PHASE (VOUT) circuit output signals are available at the circuit output terminals (32; 32') of said output drivers (31; 31') at the CMOS levels.

公开(公告)号：FR2464598A1

公开(公告)日：1981-03-06

申请号：FR7922137

申请日：1979-08-28

Applicant: IBM FRANCE

Inventor： GRANDGUILLOT MICHEL ,  MOLLIER PIERRE ,  NUEZ JEAN-PAUL

IPC: H03K19/20 ,  H03K5/151 ,  H03K19/018 ,  H03K5/15 ,  G06F1/04