公开(公告)号：GB2575598B

公开(公告)日：2021-10-06

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：GB2575598A

公开(公告)日：2020-01-15

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：GB2581116A

公开(公告)日：2020-08-05

申请号：GB202008885

申请日：2018-12-14

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：GB2581116B

公开(公告)日：2021-03-03

申请号：GB202008885

申请日：2018-12-14

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：GB2577190A

公开(公告)日：2020-03-18

申请号：GB201916582

申请日：2018-05-11

Applicant: IBM

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  VIJAY NARAYANAN ,  HEMANTH JAGANNATHAN

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal- oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.

公开(公告)号：GB2571215A

公开(公告)日：2019-08-21

申请号：GB201906829

申请日：2017-10-25

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  HEMANTH JAGANNATHAN

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/306

Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less than 500°C on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500°C for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.