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    EMITTER FOLLOWER LOGIC CIRCUIT
    1.
    发明专利
    EMITTER FOLLOWER LOGIC CIRCUIT 未知

    公开(公告)号：DE3066688D1

    公开(公告)日：1984-03-29

    申请号：DE3066688

    申请日：1980-07-10

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  HENLE ROBERT ATHANASIUS ,  KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K19/082 ,  H03K19/086 ,  H03K19/013

    Abstract: A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.

    2.
    发明专利
    未知

    公开(公告)号：DE1002540B

    公开(公告)日：1957-02-14

    申请号：DEI0009604

    申请日：1954-12-30

    Applicant: IBM DEUTSCHLAND

    Inventor： EMERY RAYMOND WALTER ,  HENLE ROBERT ATHANASIUS

    IPC: H01L29/00 ,  H03K3/35

    Abstract: 790,404. Transistor two-stable state circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1954 [Dec. 31, 1953], No. 37382/54. Class 40 (6). In a circuit employing a transistor with an auxiliary emitter, input pulses from generator 15 are applied directly to the emitter 1e and over a gate 14 to the auxiliary emitter 1a, the gate being controlled by a connection 13 from the collector 1c. Assuming the transistor to be in the off condition, the collector potential is low and due to the connection 13 the anode of diode 14 is also low. The battery 12 supplies the auxiliary emitter 1a over the resistor 11 and maintains conduction through the base 1b and the potential divider 4, 5 and 6. Diode 14 is thus effectively biased off so that an input positive pulse from generator 15 passes directly to the emitter 1e causing the transistor to pass to the on state. Since the transistor is conducting, the collector potential rises and thus the anode of diode 14. The base 1b becomes negative with respect to earth taking the electrode 1a with it while the emitter 1e is maintained near earth potential by diode 10 conducting. The next positive input pulse passes through diode 14 to electrode 1a taking the base 1b positive, the pulse applied to the emitter 1e being ineffective since the transistor is substantially saturated. The transistor is now cut-off and the circuit restores to its original condition. A capacitor 19 provides a degree of memory, making the component values less critical. Specification 790,403 is referred to.

    COMPLEMENTARY TRANSISTOR, INVERTING EMITTER FOLLOWER CIRCUIT
    3.
    发明专利
    COMPLEMENTARY TRANSISTOR, INVERTING EMITTER FOLLOWER CIRCUIT 未知

    公开(公告)号：DE3068955D1

    公开(公告)日：1984-09-20

    申请号：DE3068955

    申请日：1980-08-12

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  HENLE ROBERT ATHANASIUS ,  KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K19/086 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/66 ,  H03K19/082 ,  H03K19/20

    Abstract: A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the Vbe necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

    7.
    发明专利
    未知

    公开(公告)号：DE1026996B

    公开(公告)日：1958-03-27

    申请号：DEI0009871

    申请日：1955-02-26

    Applicant: IBM DEUTSCHLAND

    Inventor： HENLE ROBERT ATHANASIUS

    IPC: G06F7/50 ,  G06F7/502

    Abstract: 765,326. Digital electrical calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 23, 1955 [Feb. 26, 1954], No. 5398/55. Class 106 (1). An electrical binary adder comprises, for each numerical order, a sum circuit and a carry circuit each including a transistor and an output network, three input connections extending to both said transistors, the sum circuit having a normal output state and an operated output state assumed in the presence-of a signal on one of said input connections, the carry circuit having a normal output state and an operated output state assumed in the simultaneous presence of signals on at least two of said input connections, and means connecting the output network of the carry circuit to the transistor in the sum circuit and effective when the carry circuit is in its operated state to deliver to said transistor a signal of such sign and magnitude as to prevent a change of state in the sum circuit when signals are applied simultaneously to two of said input connections whilst permitting such change of state in said sum circuit when signals are applied simultaneously to all three of said input connections. The sum and carry circuits 1 and 2 respectively are both arranged as high gain amplifiers and the connecting means 50 as an inverter. In the no signal condition the three input leads 6, 7, 8 are each connected by -15 v., shown diagrammatically at 3, the sum and carry circuits are both cut-off and the inverter circuit 50 is conducting, being biased to this state by a negative voltage applied to its base via a resistor 47 from the collector circuit of the carry circuit. Upon receipt of a signal on one input line, say line 6, the voltage of line 6 rises to -5 v., causing the potential of a junction 16 to rise, and the transistor in the sum circuit conducts heavily giving an output signal across terminals 33 and 34. The carry circuit is, however, not appreciably affected by one input signal. With two input signals the carry circuit is affected and commences to conduct heavily producing an output signal across terminals 35 and 36 and, by raising the voltage on the base of the transistor in the inverter circuit, causes the inverter circuit to become non-conductive. With two input signals the sum circuit would be expected to remain conductive, but as the inverter circuit is now cut off the lowering in potential of a coupling lead 48 nullifies the rise in potential of the junction 16 due to the two input signals and the sum circuit is held non-conducting. Upon receipt of three input signals conduction in the collector circuit of the carry circuit will tend to increase, but the output signal at terminal 35 will be stabilized by a diode 23. Thus with three input signals the inverter circuit remains cutoff, the potential at junction 16 rises, and the sum circuit conducts. The apparatus thus adds signals applied to leads 6, 7, 8, and gives the sum, in binary form, at output terminals 33 and 35.

    9.
    发明专利
    未知

    公开(公告)号：DE2649356A1

    公开(公告)日：1977-07-07

    申请号：DE2649356

    申请日：1976-10-29

    Applicant: IBM

    Inventor： HENLE ROBERT ATHANASIUS ,  HO IRVING TZE

    IPC: H03F3/345 ,  H03F3/34 ,  H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0944 ,  H03F3/68 ,  G11C7/06

    Abstract: An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS CP = 2ROOT C(P-1) . C(P+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.

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