公开(公告)号：SG105511A1

公开(公告)日：2004-08-27

申请号：SG200105657

申请日：1993-02-01

Applicant: IBM

Inventor： RAJIV V JOSHI ,  JEROME J CUOMO ,  HORMAZDYAR MINOCHER DALAL ,  LOUIS L C HUS

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：GB2577210B

公开(公告)日：2022-05-11

申请号：GB201917541

申请日：2018-05-31

Applicant: IBM

Inventor： RAJIV V JOSHI ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H03B5/08 ,  H03B1/04

Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.

公开(公告)号：GB2605096A

公开(公告)日：2022-09-21

申请号：GB202208597

申请日：2020-11-18

Applicant: IBM

Inventor： STEVEN HOLMES ,  BRUCE DORIS ,  MATTHIAS GEORG GOTTWALD ,  RAJIV V JOSHI ,  SUDIPTO CHAKRABORTY

IPC: H01L39/22 ,  G11C11/44

Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.

公开(公告)号：GB2577196A

公开(公告)日：2020-03-18

申请号：GB201916879

申请日：2018-05-14

Applicant: IBM

Inventor： RAJIV V JOSHI ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H02M3/158

Abstract: Circuits and methods are disclosed for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

公开(公告)号：GB2577210A

公开(公告)日：2020-03-18

申请号：GB201917541

申请日：2018-05-31

Applicant: IBM

Inventor： RAJIV V JOSHI ,  NAIGANG WANG ,  BRUCE DORIS

IPC: H03K5/00

Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.

公开(公告)号：SG115407A1

公开(公告)日：2005-10-28

申请号：SG200105658

申请日：1993-02-01

Applicant: IBM

Inventor： RAJIV V JOSHI ,  JEROME J CUOMO ,  HORMAZDYAR MINOCHER DALAL ,  LOUIS L C HSU

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/440 ,  H01L29/460

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：SG111047A1

公开(公告)日：2005-05-30

申请号：SG200201110

申请日：1993-02-01

Applicant: IBM

Inventor： RAJIV V JOSHI ,  JEROME J CUOMO ,  HORMAZDYAR MINOCHER DALAL ,  LOUIS L HSU

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.