中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.018 seconds)

    Bus control logic computer system having dual bus architecture
    1.
    发明专利
    Bus control logic computer system having dual bus architecture 未知

    公开(公告)号：SG44430A1

    公开(公告)日：1997-12-19

    申请号：SG1996000358

    申请日：1992-12-18

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BEECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    Bus interface logic for computer system having dual bus architecture
    3.
    发明专利
    Bus interface logic for computer system having dual bus architecture 未知

    公开(公告)号：SG44432A1

    公开(公告)日：1997-12-19

    申请号：SG1996000366

    申请日：1992-12-22

    Applicant: IBM

    Inventor： ALDEREGULA ALFERDO ,  AMINI NADER ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH ,  TRAN CANG NGOC

    IPC: G06F13/16 ,  G06F13/36

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

    Bus control logic for computer system having dual bus architecture
    4.
    发明专利
    Bus control logic for computer system having dual bus architecture 未知

    公开(公告)号：AU663536B2

    公开(公告)日：1995-10-12

    申请号：AU2979292

    申请日：1992-12-02

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/14

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER
    5.
    发明专利
    BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER 未知

    公开(公告)号：NZ245344A

    公开(公告)日：1995-09-26

    申请号：NZ24534492

    申请日：1992-12-02

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERRENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16 ,  G06F15/76

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING FULL BUS ARCHITECTURE
    7.
    发明专利
    ARBITRATION CONTROL LOGIC FOR COMPUTER SYSTEM HAVING FULL BUS ARCHITECTURE 未知

    公开(公告)号：CA2080630C

    公开(公告)日：1996-10-22

    申请号：CA2080630

    申请日：1992-10-15

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/28 ,  G06F13/22 ,  G06F13/36 ,  G06F13/362 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20

    Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.

    BUS INTERFACE LOGIC FOR COMPUTER WITH DUAL BUS ARCHITECTURE
    9.
    发明专利
    BUS INTERFACE LOGIC FOR COMPUTER WITH DUAL BUS ARCHITECTURE 未知

    公开(公告)号：NZ245346A

    公开(公告)日：1995-09-26

    申请号：NZ24534692

    申请日：1992-12-02

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  AMINI NADER ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH ,  TRAN CANG NGOC

    IPC: G06F13/16 ,  G06F13/36 ,  G06F15/76

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT
    10.
    发明专利
    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT 未知

    公开(公告)号：CA2080210C

    公开(公告)日：1998-10-27

    申请号：CA2080210

    申请日：1992-10-08

    Applicant: IBM

    Inventor： LOHMAN TERENCE JOSEPH ,  AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS

    IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

    Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

Patent Agency Ranking