公开(公告)号：JPH01228038A

公开(公告)日：1989-09-12

申请号：JP31965988

申请日：1988-12-20

Applicant: IBM

Inventor： RICHIYAADO IIUIN BAAMU ,  TERII RII BOODEN ,  JIYASUTEIN RARUFU BATSUTOUERU ,  KAARU EDOWAADO KURAAKU ,  AREN JIYOOJI GANEKU ,  JIEEMUZU RAMU ,  MAIKERU JIERAADO MAARU ,  KENESU AANESUTO PURAMUBETSUKU ,  KIYASUPAA ANSONII SUKARUZUI ,  RICHIYAADO JIYON SHIYAMARUZU ,  RONARUDO MOOTON SUMISU ,  JIYURIAN TOOMASU

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/14

Abstract: PURPOSE: To block undesired access to an address space by performing the user management of address space corresponding to a token applied from a system for space identification. CONSTITUTION: An access register transform(ART) operation 10 uses contents in an access register for providing a segment table describer(STD) to be used for dynamic address translation(DAT). An instruction 12 contains an OP code, B field for designating a general-purpose register 14 containing a base address, and displacement D for generating the logical address of a storage area operand while being combined with the base address in the general-purpose register 14 through an adder 15. The STD from the ART 10 is combined with the logical address from the adder 15 and translated together by a DAT 18, and the real address of an operand to be used for the system is generated.

公开(公告)号：JPH01228039A

公开(公告)日：1989-09-12

申请号：JP31966488

申请日：1988-12-20

Applicant: IBM

Inventor： RICHIYAADO IIUIN BAAMU ,  TERII RII BOODEN ,  JIYASUTEIN RARUFU BATSUTOUERU ,  KAARU EDOWAADO KURAAKU ,  AREN JIYOOJI GANEKU ,  JIEEMUZU RAMU ,  MAIKERU JIERAADO MAARU ,  DEBUIDO RICHIYAADO PEEJI ,  KENESU AANESUTO PURAMUBETSUKU ,  KIYASUPAA ANSONII SUKARUZUI ,  RICHIYAADO JIYON SHIYAMARUZU

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24

Abstract: PURPOSE: To make permission hierarchical and non-hierarchical as well by providing a program permitting mechanism equipped with plural access registers and an access register transformation(ART) means. CONSTITUTION: An instruction 12 contains an OP code, B field for designating a general-purpose register 14 containing a base address, and displacement D for generating the logical address of a storage area operand while being combined with the base address in the general-purpose register 14 through an adder 15. An ART operation 10 uses contents in access registers 16 for providing a segment table describer (STD) to be used for dynamic address translation(DAT). When an access list entry token (AELT) is transformed by the ART 10, the STD corresponding to an address space for storing data is applied. The real address of an operand to be used for a system is generated from DAT 18.

公开(公告)号：JPS58139400A

公开(公告)日：1983-08-18

申请号：JP20222282

申请日：1982-11-19

Applicant: IBM

Inventor： JIYON RESURII BAAKU ,  JIYASUTEIN RARUFU BATSUTOUERU ,  KAARU EDOWAADO KURAAKU ,  JIYON TETSUDO RODERU ,  DEEBITSUDO EMETSUTO SUTATSUKI

IPC: G06F12/14