-
公开(公告)号:JPH01228038A
公开(公告)日:1989-09-12
申请号:JP31965988
申请日:1988-12-20
Applicant: IBM
Inventor: RICHIYAADO IIUIN BAAMU , TERII RII BOODEN , JIYASUTEIN RARUFU BATSUTOUERU , KAARU EDOWAADO KURAAKU , AREN JIYOOJI GANEKU , JIEEMUZU RAMU , MAIKERU JIERAADO MAARU , KENESU AANESUTO PURAMUBETSUKU , KIYASUPAA ANSONII SUKARUZUI , RICHIYAADO JIYON SHIYAMARUZU , RONARUDO MOOTON SUMISU , JIYURIAN TOOMASU
Abstract: PURPOSE: To block undesired access to an address space by performing the user management of address space corresponding to a token applied from a system for space identification. CONSTITUTION: An access register transform(ART) operation 10 uses contents in an access register for providing a segment table describer(STD) to be used for dynamic address translation(DAT). An instruction 12 contains an OP code, B field for designating a general-purpose register 14 containing a base address, and displacement D for generating the logical address of a storage area operand while being combined with the base address in the general-purpose register 14 through an adder 15. The STD from the ART 10 is combined with the logical address from the adder 15 and translated together by a DAT 18, and the real address of an operand to be used for the system is generated.
-
公开(公告)号:JPH0571975B2
公开(公告)日:1993-10-08
申请号:JP31866288
申请日:1988-12-19
Applicant: IBM
-
公开(公告)号:JPH01228039A
公开(公告)日:1989-09-12
申请号:JP31966488
申请日:1988-12-20
Applicant: IBM
Inventor: RICHIYAADO IIUIN BAAMU , TERII RII BOODEN , JIYASUTEIN RARUFU BATSUTOUERU , KAARU EDOWAADO KURAAKU , AREN JIYOOJI GANEKU , JIEEMUZU RAMU , MAIKERU JIERAADO MAARU , DEBUIDO RICHIYAADO PEEJI , KENESU AANESUTO PURAMUBETSUKU , KIYASUPAA ANSONII SUKARUZUI , RICHIYAADO JIYON SHIYAMARUZU
Abstract: PURPOSE: To make permission hierarchical and non-hierarchical as well by providing a program permitting mechanism equipped with plural access registers and an access register transformation(ART) means. CONSTITUTION: An instruction 12 contains an OP code, B field for designating a general-purpose register 14 containing a base address, and displacement D for generating the logical address of a storage area operand while being combined with the base address in the general-purpose register 14 through an adder 15. An ART operation 10 uses contents in access registers 16 for providing a segment table describer (STD) to be used for dynamic address translation(DAT). When an access list entry token (AELT) is transformed by the ART 10, the STD corresponding to an address space for storing data is applied. The real address of an operand to be used for a system is generated from DAT 18.
-
公开(公告)号:JPH0793183A
公开(公告)日:1995-04-07
申请号:JP19943493
申请日:1993-08-11
Applicant: IBM
Inventor: ARAN IAN ARUPAATO , KAARU EDOWAADO KURAAKU , MAIKERU HENRI TEODOA HATSUKU , KIYASUPAA ANSONII SUKARUJI , AARU JIEI SHIYUMARUTSU , BAASUKAA SHINHA
Abstract: PURPOSE: To provide a dynamic execution link between a uniquely controlled hook instruction and an analysis program. CONSTITUTION: A new dynamic execution link excludes the participation of an OS to a hook operation and excludes interruption used for linking the OS to the execution of the hook instruction. Thus, the dynamic execution link provides non-interruption connection from respective usable hook instructions to the analysis program 16 and the non-interruption connection from the analysis program 16 to a hooked program 10.
-
公开(公告)号:JPH01207856A
公开(公告)日:1989-08-21
申请号:JP31866288
申请日:1988-12-19
Applicant: IBM
Inventor: KAARU EDOWAADO KURAAKU , AREN JIYOOJI GAANEKU , MAIKERU JIERAADO MAARU , DEBUIDO RICHIYAADO PEEJI
Abstract: PURPOSE: To separate system control over an address space from program control by an access register by selecting a specific entry in a 1st or 2nd access list by using a token that the access register includes. CONSTITUTION: The access register 22 corresponding to a general register 20 includes the token for address space discrimination. Dynamic address conversion 18 using the operand in the register 20 is performed for the address space indicated by the token. Further, a process which obtains a segment table descriptor 98 by using the access register conversion 30 consists of two steps, and the token is used first to discriminate between a 2nd table entry and an entry in an access list. Then a 2nd entry address is used to access a 2nd entry including the descriptor 98 used for the conversion 18. Consequently, the control over the address space can be separated from the control by the access register.
-
公开(公告)号:JPH0683710A
公开(公告)日:1994-03-25
申请号:JP691593
申请日:1993-01-19
Applicant: IBM
Inventor: KAARU EDOWAADO KURAAKU , JIEFUREI ARAN FUREI , KENESU AANESUTO PURAMUBETSUKU , KIYASUPAA ANSONII SUKARUZUI , BAASUKAA SHINHA
Abstract: PURPOSE: To provide an efficient inter-space branch process to separated programs in different address spaces in a group of related address spaces of a subsystem. CONSTITUTION: The group has a fundamental space and at least one partial space, and each partial space can include a program and data, which cannot be accessed from other partial spaces, to separate the program and data in a subsystem. Any CPU in a computer system can designate programs found in address spaces. A designating process checks authority for access to the group of a user of the group and executes an intra-group program call instruction which designates first and second general registers.
-
公开(公告)号:JPH0683625A
公开(公告)日:1994-03-25
申请号:JP489093
申请日:1993-01-14
Applicant: IBM
Inventor: ARAN IAN ARUPAATO , KAARU EDOWAADO KURAAKU , JIEFURII ARAN FUREI , MAIKERU JIERARUDO MOORU
Abstract: PURPOSE: To provide a PROGRAM CALL for the reference space of a task designation enabling unit. CONSTITUTION: A reference space is identified, and one reference address space parameter or more are retrieved from a DUCT to be used at the time of performing access to corresponding control information positioned in a second table 602 of an address space number. A BASTEO 504 is retrieved from a DUCT 500, and 6 zeros are added to the right side of the BASTEO for forming an actual address at the time of obtaining an entry 604 (ASTE) of the table 602. A permission index (AX) 606 of the ASTE and a BASN 508 are respectively placed in a control register 4 of a 608 (AX) and a 610 (PASN), a segment table indication 612 of the ASTE is placed in a control register 1 of a PSTD 614, and an actual SDTE address is placed in a control register 5 of a 616 as a PASTEO. The entry of the second table of an ASN is obtained by using a BASTEO positioned at the DUCT.
-
公开(公告)号:JPS58139400A
公开(公告)日:1983-08-18
申请号:JP20222282
申请日:1982-11-19
Applicant: IBM
Inventor: JIYON RESURII BAAKU , JIYASUTEIN RARUFU BATSUTOUERU , KAARU EDOWAADO KURAAKU , JIYON TETSUDO RODERU , DEEBITSUDO EMETSUTO SUTATSUKI
IPC: G06F12/14
-
公开(公告)号:JPH05204762A
公开(公告)日:1993-08-13
申请号:JP10647392
申请日:1992-04-24
Applicant: IBM
Inventor: KAARU EDOWAADO KURAAKU , MAIKERU JIERAADO MOORU , KIYASUPAA ANSONII SUKARUJI , BASUKA SHINHA
Abstract: PURPOSE: To make it possible to expand the level of protection of a protection key for memory storage which can be controlled by programming by adding a 3rd protection level. CONSTITUTION: An array 22 of protection keys contains three storage protection keys of an administrative class, an intermediate class, and a general class. A program routine which is operated with the access key of the administrative key can access all the storage blocks in the main storage 21. A program routine operating with the access key of the intermediate level can not access the storage blocks of the administrative level, but can access storage blocks to which the keys of the general and intermediate levels are assigned. With the program access key using a general storage key (PSK) of the 3rd level, only blocks having the same PSK value can be accessed.
-
公开(公告)号:JPH01228027A
公开(公告)日:1989-09-12
申请号:JP31965788
申请日:1988-12-20
Applicant: IBM
Inventor: KAARU EDOWAADO KURAAKU
Abstract: PURPOSE: To efficiently access instructions and data in multiple address spaces by setting an address space control bit in a program condition word(PSW) a home mode. CONSTITUTION: A home space mechanism is provided with a home segment table describer(HSTD) in a control register 13 and provided with an address space control(ASC) bit 34 for designating a home space mode in the PSW. Further, when a CPU is set in the home space mode before or after an operation with the completion of ASC setting, the home space mechanism provided with a means for recognizing a space switching event and a home space switching event control bit makes it possible for an operating system basic control program (CP) in a home space to perform service to the other address space without mapping a CP code into all the address spaces.
-
-
-
-
-
-
-
-
-