公开(公告)号：JP2005260228A

公开(公告)日：2005-09-22

申请号：JP2005059899

申请日：2005-03-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAMACHANDORA DEIVAKARUNI ,  GLUSCHENKOV OLEG ,  KWON OH-JUNG ,  RAJEEV MALIK

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure to resolve problems in word line continuity and support region punch-through, and to provide a manufacturing method therefor. SOLUTION: An integrated circuit comprises at least one semiconductor memory array and a logic circuit. The memory array includes conductive word lines. The logic circuit includes a logic transistor having a conductive gate. The gate of the logic transistor and the word lines are composed of polysilicon and metal layers. In the word lines, the metal layer is thicker than the polysilicon layer. In the gate of the logic transistor, the metal layer is thinner than the polysilicon layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供解决字线连续性和支撑区域穿透中的问题的结构，并提供其制造方法。 解决方案：集成电路包括至少一个半导体存储器阵列和逻辑电路。 存储器阵列包括导电字线。 逻辑电路包括具有导电栅极的逻辑晶体管。 逻辑晶体管的栅极和字线由多晶硅和金属层组成。 在字线中，金属层比多晶硅层厚。 在逻辑晶体管的栅极中，金属层比多晶硅层薄。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002026147A

公开(公告)日：2002-01-25

申请号：JP2001189079

申请日：2001-06-22

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  KAARU JIEI RADENSU ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure including a planar semiconductor substrate. SOLUTION: The semiconductor substrate has a deep trench. The deep trench has side walls and one bottom part. A storage capacitor is located at the bottom of the deep trench. On at least one sidewall of the deep trench, a vertical transistor extends downwardly. This transistor has source diffusion extending in the plane of the substrate adjacent to the deep trench. On at least the other sidewall of the deep trench on the opposite side from the vertical transistor, a separation part extends downwardly. A shallow trench separation area extends laterally to the sidewall, where the vertical transistor extends along the surface of the substrate. In the inside of the deep trench, a gate conductor extends. A word line extends onto the deep trench and is connected to the gate conductor. The bit line extends onto the surface of the substrate and has a contact for the source diffusion between shallow trench separation areas.

公开(公告)号：JP2004128489A

公开(公告)日：2004-04-22

申请号：JP2003310714

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RADENS CARL J ,  RAMACHANDORA DEIVAKARUNI ,  MANDELMAN JACK A

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To make the interaction between straps smaller than that of the conventional ones. SOLUTION: Each deep trench has its rim in a direction orthogonal to its depth direction. A buried strap 60 extends along the rim. The length of the buried strap 60 is limited to 5-20% of the full length of the rim, and is smaller than one lithography feature size. The buried strap 60, which lies along the rim, is preferably curved and positioned along only one corner of the rim. This structure is useful especially for sub-8F 2 cells. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004088098A

公开(公告)日：2004-03-18

申请号：JP2003287154

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL P ,  BEINTNER JOCHEN ,  RAMACHANDORA DEIVAKARUNI ,  JAMMY RAJARAO

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method to form a three-dimensional electrical structure which brings two circuit elements separated in the horizontal and vertical directions into contact, regarding the formation of structures including a DRAM cell comprising a vertical transistor.
SOLUTION: A temporary insulator layer is deposited, and a vertical spacer is formed on the trench walls above the temporary insulator, then the insulator is removed to expose the substrate walls. Next, dopant is diffused into the substrate walls to form a self-aligned extension of a buried strap, and a final gate insulator is deposited, then the upper portion of a DRAM cell is formed.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.

公开(公告)号：JP2001345383A

公开(公告)日：2001-12-14

申请号：JP2001160548

申请日：2001-05-29

Applicant: IBM

Inventor： CLAUDEL L BARTIN ,  RAMACHANDORA DEIVAKARUNI ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an anti-fuse structure which can program at a low voltage and current, uses only in an extremely small chip base, and can be formed in a gap between parts which are disposed at intervals of a least lithographic feature size. SOLUTION: An anti-fuse structure is formed on an SOI substrate in combination with a capacitor-like structure which reaches support layer or in the support layer by etching a contact which penetrates an insulator and reaches the support semiconductor layer. This anti-fuse can be programmed by selecting a position forming a conductor or damaging a dielectric of the capacitor-like structure. It is possible to restrict the damages to a desirable position by use of an insulation collar enclosing the conductor or a part of the capacitor-like structure. Thermal influences due to a programming current are isolated into the interior of a bulk silicon layer, whereby a programming during a normal operation of a device is enabled.

公开(公告)号：JP2006041516A

公开(公告)日：2006-02-09

申请号：JP2005208400

申请日：2005-07-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDORA DEIVAKARUNI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for forming strained and non-strained areas on one substrate. SOLUTION: A disclosed method comprises: a process of forming a pattern of strained and relaxed materials on a substrate 101; a process of forming a strained device 129 in the strained material; and a process of forming a non-strained device 131 in the relaxed material. The strained material is silicon (Si) in a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer 113 which is made of silicon germanium (SiGe), silicon carbon (SiC), or a similar material and has a different lattice constant/structure from that of the substrate, and a relaxed layer 111 are formed on the substrate 101. The strained material is placed in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multilayer substrate having strained and non-strained materials on which a pattern is formed. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供在一个基板上形成应变和非应变区域的方法和结构。 解决方案：所公开的方法包括：在衬底101上形成应变和松弛材料的图案的工艺; 在应变材料中形成应变器件129的工艺; 以及在松弛材料中形成非应变器件131的工艺。 应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是Si处于正常状态。 在衬底101上形成由硅锗（SiGe），硅碳（SiC）或类似材料制成并且具有与衬底的晶格常数/结构不同的晶格常数/结构的缓冲层113。 应变材料处于拉伸或压缩状态。 在另一个实施例中，使用碳掺杂硅或锗掺杂硅来形成应变材料。 该结构包括具有应变和非应变材料的多层基底，其上形成图案。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004040095A

公开(公告)日：2004-02-05

申请号：JP2003178790

申请日：2003-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  YANG HAINING

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM array employing a small vertical transistor of bitline capacitance. SOLUTION: A DRAM array comprising DRAM cells employing the vertical transistor increases electrical reliability and reduces the bitline capacitance by the use of an asymmetric structure in connection between a wordline 310 and the transistor. Thereby, the DRAM array permits the use of wider connection between the wordline 310 and a transistor electrode. Also, the word line 310 is used as an etch stop to protect a transistor gate 205 during the patterning of the wordline 310. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002134631A

公开(公告)日：2002-05-10

申请号：JP2001300150

申请日：2001-09-28

Applicant: IBM

Inventor： ADKISSON JAMES W ,  RAMACHANDORA DEIVAKARUNI ,  JEFFREY P GANBINO ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that comprises an embedded DRAM device and a logic device, and to provide a its manufacturing method. SOLUTION: This device comprises a monocrystal substrate having an almost flat surface, a first surface region on the flat surface having a silicon on insulator region, a second surface region on the flat surface which is a monocrystal bulk region, an embeded logic device which is formed in the silicon on insulator region, an embedded memory device which is formed in the monocrystal bulk region, and a trench in the bulk monocrystal region.

公开(公告)号：JP2005051246A

公开(公告)日：2005-02-24

申请号：JP2004222267

申请日：2004-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDORA DEIVAKARUNI ,  SUNG C Y

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02

CPC classification number: H01L27/10876 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/1087 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for a vertical DRAM device having a self-aligning function of shaping upper trench. SOLUTION: The method and the structure of a memory storage cell in a semiconductor substrate include forming of a dopant source material, covering a lower portion of a deep trench formed in the substrate. The upper portion of the trench is generally shaped into a rectangular form, and an embedded electrode plate of a trench capacitor by annealing the dopant source material. The embedded electrode plate is self-aligned, with respect to the shaped upper-portion of the trench. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种具有成形上沟槽自对准功能的垂直DRAM器件的方法和结构。 解决方案：半导体衬底中的存储器存储单元的方法和结构包括形成掺杂剂源材料，覆盖形成在衬底中的深沟槽的下部。 沟槽的上部通常通过对掺杂剂源材料进行退火而成形为矩形形状，以及沟槽电容器的嵌入式电极板。 嵌入式电极板相对于沟槽的成形上部自对准。 版权所有（C）2005，JPO＆NCIPI