公开(公告)号：EP2022085A4

公开(公告)日：2011-08-03

申请号：EP07755161

申请日：2007-04-10

Applicant: IBM

Inventor： FANG SUNFEI ,  KNARR RANDOLPH F ,  KRISHNAN MAHADEVAIYER ,  LAVOIE CHRISTIAN ,  MO RENEE T ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  STRANE JAY W

IPC: H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

公开(公告)号：JP2005057264A

公开(公告)日：2005-03-03

申请号：JP2004218340

申请日：2004-07-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG TIEN-JEN ,  EICHSTADT DAVID E ,  GRIFFITH JONATHAN H ,  KNARR RANDOLPH F ,  PETRARCA KEVIN S ,  QUON ROGER A

IPC: H01L21/60 ,  H01L21/44 ,  H01L23/48 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K3/3457 ,  H05K3/4007 ,  H01L2224/05099

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing fine pitch electric conduction pads for flip chip bonding (also referred to as bumps). SOLUTION: Solder bumps which connect an electron device with a substrate or another structure are formed, by plating copper pins of high aspect ratio on a supporting structure, enclosing the pins into barrier materials, plating over the barrier materials with solders, and then, reflowing the solders. This electric structure includes electrical connection members fitted so as to connect with another electric structure. The structure comprises a set of contacts in the electric structure, at least one interface layer attaching to the set of contacts, a set of pads which are disposed on the set of contacts and include the interface layer, a set of electric conduction pins directly attaching to the pads, barrier layers attaching to all exposure surfaces of the set of the pins, and solder layers which enclose the barrier layers. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于倒装芯片接合的细间距导电焊盘的方法（也称为凸块）。 解决方案：通过在支撑结构上镀覆高纵横比的铜销将电子器件与衬底或其他结构连接起来的焊料凸块，将引脚封装成阻挡材料，用焊料覆盖阻隔材料，以及 然后，回流焊接。 这种电气结构包括电连接构件，其被安装成与另一个电气结构连接。 该结构包括在电结构中的一组触点，至少一个界面层，附着到该组触点，一组焊盘，它们设置在触点组上，并包括界面层，一组导电引脚直接连接 连接到该组引脚的所有暴露表面的焊盘，阻挡层以及围绕阻挡层的焊料层。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005094013A

公开(公告)日：2005-04-07

申请号：JP2004269142

申请日：2004-09-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BIGGS JULIE C ,  CHENG TIEN-JEN ,  EICHSTADT DAVID E ,  FANTI LISA A ,  GRIFFITH JONATHAN H ,  KNARR RANDOLPH F ,  KNICKERBOCKER SARAH H ,  PETRARCA KEVIN S ,  QUON ROGER A ,  SAUTER WOLFGANG ,  SRIVASTAVA KAMALESH K ,  VOLANT RICHARD P

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a wire bond in an I/C chip. SOLUTION: This method comprises steps of: providing an I/C chip having a conductive pad for wire bonding and at least one dielectric material layer on the pad; forming an opening penetrating the dielectric material layer to expose a part of said pad; forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening; forming a seed layer on the first conductive layer, applying photoresist onto the seed layer; exposing the photoresist to light and developing the light-exposed photoresist; exposing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material inside the opening to expose the seed layer; coating at least one second conductive material layer on the seed layer inside the opening; and removing the first conductive layer on the dielectric layer around the opening. The present invention includes the structure obtained by the above method. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在I / C芯片中形成引线键合的方法。 解决方案：该方法包括以下步骤：提供具有用于引线接合的导电焊盘和衬垫上的至少一个电介质材料层的I / C芯片; 形成贯穿所述电介质材料层的开口以露出所述垫的一部分; 在所述垫的暴露表面和所述开口的表面上形成至少第一导电层; 在所述第一导电层上形成种子层，将光致抗蚀剂施加到种子层上; 将光致抗蚀剂曝光并显影曝光的光致抗蚀剂; 暴露围绕开口的种子层的表面; 去除暴露的种子层; 去除开口内的光致抗蚀剂材料以暴露种子层; 在开口内的种子层上涂覆至少一个第二导电材料层; 以及去除围绕开口的电介质层上的第一导电层。 本发明包括通过上述方法获得的结构。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007112361A3

公开(公告)日：2008-04-10

申请号：PCT/US2007064946

申请日：2007-03-26

Applicant: IBM ,  CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

Inventor： CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

IPC: H01L29/02

CPC classification number: H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a suicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the suicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Abstract translation: 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的自杀或锗化物层，例如钴和/或镍; 接触层包括位于介电层顶部并且在空腔内并且与底部上的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。