公开(公告)号：EP1800335A4

公开(公告)日：2008-01-02

申请号：EP05797431

申请日：2005-09-20

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL ,  RODBELL KENNETH P

IPC: H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer (440). The impure copper seed layer (440) covers a barrier layer (230), which covers an insulating layer (115) that has an opening. Electroplated copper fills the opening in the insulating layer (115). Through a chemical mechanical polish, the barrier layer (230), the impure copper seed layer (440) derived from an electroplated copper bath, and the electroplated copper are planarized to the insulating layer (115).

公开(公告)号：EP1841558A4

公开(公告)日：2012-04-04

申请号：EP05852628

申请日：2005-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER ENAMUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00 ,  B23H5/08

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

公开(公告)号：EP2022085A4

公开(公告)日：2011-08-03

申请号：EP07755161

申请日：2007-04-10

Applicant: IBM

Inventor： FANG SUNFEI ,  KNARR RANDOLPH F ,  KRISHNAN MAHADEVAIYER ,  LAVOIE CHRISTIAN ,  MO RENEE T ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  STRANE JAY W

IPC: H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

公开(公告)号：JP2004146800A

公开(公告)日：2004-05-20

申请号：JP2003313299

申请日：2003-09-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CANAPERI DONALD F ,  DALTON TIMOTHY J ,  GATES STEPHEN M ,  KRISHNAN MAHADEVAIYER ,  PURUSHOTHAMAN SAMPATH ,  SMITH SEAN P E ,  NITTA SATYA

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which realizes high performance interconnection including copper wiring and an insulator having an extremely low dielectric constant (k). SOLUTION: In this structure, wiring is supported by a low-k dielectric material having relatively high durability, such as SiLk(R) or SiO 2 , and then the remaining spaces in the structure are filled with a gap filling dielectric material that has an extremely low-k and a small hardness. Accordingly, in the structure, durable layers for obtaining the strength are bonded with an extremely low-k dielectric material for achieving electric performance of the interconnection. As a result, damages to and an increase in dielectric constant of the extremely low-k dielectric material caused during the manufacturing process are avoided, and delamination in the structure during the metal chemical mechanical polishing processes is prevented. Further, photoresist poisoning troubles caused by interaction with the extremely low-k dielectric material can be removed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004200684A

公开(公告)日：2004-07-15

申请号：JP2003413888

申请日：2003-12-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  DALTON TIMOTHY J ,  DAVIS KENNETH M ,  HU CHAO-KUN ,  JAMIN FEN F ,  KALDOR STEFFEN K ,  KRISHNAN MAHADEVAIYER ,  KUMAR KAUSHIK ,  MICHAEL F ROFARO ,  SANDRA G MARUHOTORA

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure of an integrated circuit having a logic/functional device layer and an interconnection layer above it. SOLUTION: This interconnection layer has a substrate, a conductive feature 122 in the substrate, and a cap 151 which is formed only above the conductive feature. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2012047780A3

公开(公告)日：2012-06-14

申请号：PCT/US2011054545

申请日：2011-10-03

Applicant: IBM ,  ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON ,  HUPKA JUKASZ J ,  KOLI DINESH R ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

Inventor： ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON ,  HUPKA JUKASZ J ,  KOLI DINESH R ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/336 ,  H01L21/304 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

Abstract translation: 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

公开(公告)号：WO2012047770A3

公开(公告)日：2012-06-21

申请号：PCT/US2011054521

申请日：2011-10-03

Applicant: IBM ,  CHANG JOSEPHINE B ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL A ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

Inventor： CHANG JOSEPHINE B ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL A ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Abstract translation: 平面化方法包括在第一化学机械抛光步骤中平坦化半导体晶片以去除覆盖层并平坦化顶层，从而在顶层之上留下厚度的顶层材料。 顶层材料在第二化学机械抛光步骤中被平坦化，以进一步去除顶层并暴露第二材料和第三材料的下层，使得顶层材料对第二材料对第三材料的选择性在 约1：1至约2：1：1，以提供平面形貌。

公开(公告)号：WO2006088533A3

公开(公告)日：2007-09-27

申请号：PCT/US2005043464

申请日：2005-12-02

Applicant: IBM ,  ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract translation: 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：GB2497253A

公开(公告)日：2013-06-05

申请号：GB201305907

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： ANDO TAKASHI ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  HUPKA JUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

公开(公告)号：DE60311131D1

公开(公告)日：2007-02-22

申请号：DE60311131

申请日：2003-11-05

Applicant: QIMONDA AG ,  IBM

Inventor： COSTRINI GREG ,  HUMMEL P ,  KRISHNAN MAHADEVAIYER ,  LOW KIA-SENG

IPC: G11C11/16 ,  H01F10/26 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L43/12

Abstract: A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.