公开(公告)号：EP1825508A4

公开(公告)日：2009-06-24

申请号：EP05852638

申请日：2005-12-01

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

公开(公告)号：EP1941545A4

公开(公告)日：2011-03-30

申请号：EP06825349

申请日：2006-10-03

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

IPC: H01L23/58 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2022085A4

公开(公告)日：2011-08-03

申请号：EP07755161

申请日：2007-04-10

Applicant: IBM

Inventor： FANG SUNFEI ,  KNARR RANDOLPH F ,  KRISHNAN MAHADEVAIYER ,  LAVOIE CHRISTIAN ,  MO RENEE T ,  PRANATHARTHIHARAN BALASUBRAMANIAN ,  STRANE JAY W

IPC: H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

公开(公告)号：EP1831925A4

公开(公告)日：2009-06-24

申请号：EP05852637

申请日：2005-12-01

Applicant: IBM

Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

公开(公告)号：JP2005167251A

公开(公告)日：2005-06-23

申请号：JP2004349278

申请日：2004-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CYRILLE CABRAL JR ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LAVOIE CHRISTIAN ,  NARAYANAN VIJAY ,  STEEGEN AN L

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823835

Abstract: PROBLEM TO BE SOLVED: To minimize the associated complexity and cost in fabricating a CMOS structure containing silicide contacts and metal silicide gates.
SOLUTION: The method of integrating the silicide metal of a CMOS allows incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-alignment process (salicide) and at least one lithography process. The integration method allows at least two different thicknesses of metals deposited on a semiconductor substrate such that on some of the CMOS transistors thinner silicide metals are formed and used in the formation of gate contacts, whereas on the other CMOS transistors thicker silicide metals are formed and used in the formation of metal silicide gates. The integration method of the present invention can also be used to form multiple phases of metal silicide gates by varying the metal deposition thickness thus having differing amounts of metal present during metal gate formation.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了最小化制造包含硅化物接触和金属硅化物栅极的CMOS结构的相关复杂性和成本。 解决方案：集成CMOS的硅化物金属的方法允许使用自对准工艺（自对准硅化物）和至少一个光刻工艺并入硅化物触点（S / D和栅极）和金属硅化物栅极。 积分方法允许沉积在半导体衬底上的至少两种不同厚度的金属，使得在一些CMOS晶体管上形成较薄的硅化物金属，并用于形成栅极触点，而在另一个CMOS晶体管上形成更厚的硅化物金属， 用于形成金属硅化物门。 本发明的积分方法还可用于通过改变金属沉积厚度从而在金属栅极形成期间存在不同量的金属来形成金属硅化物栅极的多相。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2007318132A

公开(公告)日：2007-12-06

申请号：JP2007130825

申请日：2007-05-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MURRAY CONAL EUGENE ,  LAVOIE CHRISTIAN ,  RODBELL KENNETH P

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

CPC classification number: H01L23/485 ,  H01L21/28518 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure of reducing the contact resistance between a silicide contact and metallization on it. SOLUTION: A structure is provided with: a semiconductor substrate 12 including at least one field effect transistor arranged on the top and including silicide contact regions 16A, 16B, and 16C arranged adjacent to at least one field effect transistor; an insulating intermediate layer 18 that is arranged on the semiconductor substrate, extended onto at least one field effect transistor, and having contact opening parts 20 exposing the silicide contact regions; and a contact material 24 containing metal germanide in the contact opening parts. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供减少硅化物接触和金属化之间的接触电阻的方法和结构。 解决方案：一种结构设置有：半导体衬底12，包括布置在顶部上的至少一个场效应晶体管，并且包括与至少一个场效应晶体管相邻布置的硅化物接触区域16A，16B和16C; 布置在半导体衬底上的绝缘中间层18延伸到至少一个场效应晶体管上，并且具有暴露硅化物接触区域的接触开口部分20; 以及在接触开口部分中含有金属锗化物的接触材料24。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002353246A

公开(公告)日：2002-12-06

申请号：JP2002110367

申请日：2002-04-12

Applicant: IBM

Inventor： CYRILLE CABRAL JR ,  KEVIN K CHAN ,  COHEN GUY MOSHE ,  GUARINI KATHRYN WILDER ,  LAVOIE CHRISTIAN ,  PAUL MICHAEL SOLOMON ,  ZHANG YING

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.

公开(公告)号：WO2006060574A3

公开(公告)日：2006-07-20

申请号：PCT/US2005043473

申请日：2005-12-01

Applicant: IBM ,  FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

Inventor： FANG SUNFEI ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  LAVOIE CHRISTIAN ,  WANN CLEMENT H

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device (270) having a first well region (253) in a semiconductor substrate (252), first source/drain silicide areas (266) in the first well region (253), and a first type gate (263) isolated from the first source/drain silicide areas (266); forming a second type semiconductor device (280) having a second well region (254) in the semiconductor substrate (252), second source/drain silicide areas (256) in the second well region (254), and a second type gate (258) isolated from the second source/drain silicide areas (256); selectively forming a first metal layer (218) over the second type semiconductor device (280); performing a first fully silicided (FUSI) gate formation on only the second type gate (258); depositing a second metal layer (275) over the first and second type semiconductor devices (270,280); and performing a second FUSI gate formation on only the first type gate (263).

Abstract translation: 一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅极的方法，其中该方法包括在半导体衬底（252）中形成具有第一阱区（253）的第一类型半导体器件（270） ，第一阱区（253）中的第一源极/漏极硅化物区域（266）以及与第一源极/漏极硅化物区域（266）隔离的第一类型栅极（263）; 形成具有半导体衬底（252）中的第二阱区（254），第二阱区（254）中的第二源极/漏极硅化物区（256）和第二类型栅极（258）的第二类型半导体器件 ）与第二源极/漏极硅化物区域（256）隔离; 在所述第二类型半导体器件（280）上方选择性地形成第一金属层（218）; 仅在所述第二类型栅极（258）上执行第一全硅化物（FUSI）栅极形成; 在第一和第二类型半导体器件（270,280）上沉积第二金属层（275）; 以及仅在第一类型栅极（263）上执行第二FUSI栅极形成。

公开(公告)号：WO2007044305A3

公开(公告)日：2007-12-13

申请号：PCT/US2006038475

申请日：2006-10-03

Applicant: IBM ,  YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

Inventor： YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

IPC: H01L23/58

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

Abstract translation: 提供了一种互连结构，该互连结构包括具有增强的导电材料（优选Cu）扩散性质的镀敷种子层，其消除了使用单独的扩散层和种子层的需要。 具体而言，本发明提供用于互连金属扩散增强的镀敷种子层内的氧/氮过渡区。 电镀种子层可以包括Ru，Ir或其合金，互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等等。 优选地，互连导电材料是Cu或AlCu。 更具体地说，本发明提供了包括夹在顶部和底部种子区之间的氧/氮过渡区的单种晶层。 电镀种子层内氧/氮过渡区的存在显着增强了电镀种子的扩散阻挡性。

公开(公告)号：WO2011056313A3

公开(公告)日：2011-08-18

申请号：PCT/US2010049901

申请日：2010-09-23

Applicant: IBM ,  OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

Inventor： OZCAN AHMET S ,  LAVOIE CHRISTIAN ,  DOMENICUCCI ANTHONY G

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6659

Abstract: An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a suicide region comprising Pt segregated in a region of the suicide away from the top surface of the suicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the suicide. The suicide is first formed by a formation anneal, at a temperature in the range 250°C to 450°C. Subsequently, a segregation anneal at a temperature in the range 450°C to 550°C. The distribution of the Pt along the vertical length of the suicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the suicide layer and the pulldown spacer height.

Abstract translation: 提供集成电路，其包括具有小于或等于65nm的宽度的窄栅极叠层，包括硅化物区域，该硅化物区域包括在远离硅化物顶表面的硅化物区域中偏析的Pt以及朝向由 在栅极导体的侧壁上的间隔物的下拉高度。 在一个优选实施例中，在形成硅化物之前将隔离物拉下。 该硅化物首先通过形成退火在250℃至450℃的温度下形成。 随后，在450℃至550℃的温度下进行偏析退火。 沿着硅化物层的垂直长度的Pt的分布在分离区域内具有峰值Pt浓度，并且分离的Pt区域具有在峰值Pt浓度的一半处的宽度，其小于顶部表面之间的距离的50％ 的硅化层和下拉间隔物高度。